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VME64x core
Commit 05346fed authored by dpedrett's avatar dpedrett
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RST_i signal removed from VME64xCore_Top, add odd parity control, default… 

RST_i signal removed from VME64xCore_Top, add odd parity control, default configuration: WB Data bus 32 bit, module disabled

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@151 665b4545-5c6b-4c24-801b-41150b02b44b
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hdl/boards/svec/rtl/IRQ_generator.vhd 0 → 100644
View file @ 05346fed
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: IRQ_generator.vhd
--_____________________________________________________________________________
-- Description: This block generates an interrupt request; the interrupt request
-- is a pulse on the WB bus slave1_o.int line. The Interrupt frequency is setted
-- by the VME Master writing the FREQ register:
-- Values refer to a 20 MHz clock:
-- | FREQ values: | Time between 2 consecutive interrupts: |
-- | 0x00000000 | NO interrupt (default value) |
-- | 0x08000000 | Interrupt any 6,72 s |
-- | 0x04000000 | Interrupt any 3,36 s |
-- | 0x02000000 | Interrupt any 1,67 s |
-- | 0x01000000 | Interrupt any 0,83 s |
-- | 0x00800000 | Interrupt any 0,42 s |
-- | 0x00400000 | Interrupt any 0,20 s |
-- | 0x00200000 | Interrupt any 0,10 s |
-- | 0x00100000 | Interrupt any 0,05 s |
-- | 0x00080000 | Interrupt any 26 ms |
-- | 0x00040000 | Interrupt any 13 ms |
-- | 0x00020000 | Interrupt any 7 ms |
-- | 0x00010000 | Interrupt any 3 ms |
-- | 0x00008000 | Interrupt any 1,6 ms |
-- | 0x00004000 | Interrupt any 0,8 ms |
-- | 0x00002000 | Interrupt any 0,4 ms |
-- | 0x00001000 | Interrupt any 0,2 ms |
-- | 0x00000800 | Interrupt any 102 us |
-- | 0x00000400 | Interrupt any 50 us |
-- | 0x00000200 | Interrupt any 25 us |
-- | 0x00000100 | Interrupt any 13 us |
-- | 0x00000080 | Interrupt any 6,4 us |
-- | 0x00000040 | Interrupt any 3,2 us |
-- | 0x00000020 | Interrupt any 1,6 us |
-- | 0x00000010 | Interrupt any 800 ns |
--
-- The IRQ Generator can't generate a new interrupt request before the
-- VME Master read the INT_COUNT register! This operation should be the
-- last operation in the Interrupt service routine.
-- The Master reading the INT_COUNT register can check if it is missing some
-- interrupts; eg if the Master read 0x01, 0x05, 0x09 it means that
-- the Interrupt frequency should be lowered by writing the FREQ register.
--
-- Finite State Machine:
-- ___________ ___________ ____________ ____________
-- | IDLE |--->| CHECK |--->| INCR |--->| IRQ |--->
-- |___________| |___________| |____________| |____________| |
-- | |
-- | ________________ _______________ |
-- |<----------------| WAIT_RD |<----| WAIT_INT_ACK |<----
-- |________________| |_______________|
--
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IRQ_generator is
Port ( clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector (31 downto 0);
Int_Count_i : in std_logic_vector (31 downto 0);
Read_Int_Count : in std_logic;
INT_ack : in std_logic;
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector (31 downto 0));
end IRQ_generator;
architecture Behavioral of IRQ_generator is
type t_FSM is (IDLE, CHECK, INCR, IRQ, WAIT_INT_ACK, WAIT_RD);
signal s_en_int : std_logic;
signal currs, nexts : t_FSM;
signal s_IRQ_o : std_logic;
signal s_count : unsigned(31 downto 0);
signal s_Rd_Int_Count_delayed : std_logic;
signal s_pulse : std_logic;
signal s_count_int : unsigned(31 downto 0);
signal s_count_req : unsigned(31 downto 0);
signal s_incr : std_logic;
signal s_gen_irq : std_logic;
signal s_count0 : std_logic;
signal s_Freq : std_logic_vector(31 downto 0);
begin
-- In/Out sample
RDinputSample : entity work.DoubleSigInputSample
port map(
sig_i => Read_Int_Count,
sig_o => s_Rd_Int_Count_delayed,
clk_i => clk_i
);
IRQOutputSample : entity work.FlipFlopD
port map(
sig_i => s_IRQ_o,
sig_o => IRQ_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
-- Upload s_Freq signal; this operation should be done when the
-- internal count is 0 because the VME Master can change the FREQ
-- register at any time.
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then s_Freq <= (others => '0');
elsif s_count0 = '1' then
s_Freq <= Freq;
end if;
end if;
end process;
-- check if s_count is 0
process(clk_i)
begin
if rising_edge(clk_i) then
if s_count = 0 then
s_count0 <= '1';
else
s_count0 <= '0';
end if;
end if;
end process;
--if FREQ = 0x00000000 --> No interrupt
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then s_en_int <= '0';
elsif unsigned(s_Freq) = 0 then
s_en_int <= '0';
else
s_en_int <= '1';
end if;
end if;
end process;
--Counter
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' or s_pulse = '1' then
s_count <= (others => '0');
elsif s_en_int = '1' then
s_count <= s_count + 1;
end if;
end if;
end process;
-- Interrupt pulse generator
process(clk_i)
begin
if rising_edge(clk_i) then
if s_en_int = '1' and unsigned(s_Freq) = s_count then
s_pulse <= '1';
else
s_pulse <= '0';
end if;
end if;
end process;
--Counter interrupt pulse --> to INT_COUNT register
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
s_count_int <= (others => '0');
elsif s_en_int = '1' and s_pulse = '1' then
s_count_int <= s_count_int + 1;
end if;
end if;
end process;
--Counter interrupt requests
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
s_count_req <= (others => '0');
elsif s_incr = '1' then
s_count_req <= s_count_req + 1;
end if;
end if;
end process;
-- if INT_COUNT > Interrupt requests than generate an interrupt request
process(clk_i)
begin
if rising_edge(clk_i) then
if unsigned(Int_Count_i) > s_count_req then
s_gen_irq <= '1';
else
s_gen_irq <= '0';
end if;
end if;
end process;
-- Update current state
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then currs <= IDLE;
else currs <= nexts;
end if;
end if;
end process;
-- generate next state
process(currs,s_gen_irq,INT_ack,s_Rd_Int_Count_delayed)
begin
case currs is
when IDLE =>
nexts <= CHECK;
when CHECK =>
if s_gen_irq = '1' then
nexts <= INCR;
else
nexts <= CHECK;
end if;
when INCR =>
nexts <= IRQ;
when IRQ =>
nexts <= WAIT_INT_ACK;
when WAIT_INT_ACK =>
if INT_ack = '0' then
nexts <= WAIT_RD;
else
nexts <= WAIT_INT_ACK;
end if;
when WAIT_RD =>
if s_Rd_Int_Count_delayed = '1' then
nexts <= IDLE;
else
nexts <= WAIT_RD;
end if;
end case;
end process;
-- Update outputs
process(currs)
begin
case currs is
when IDLE =>
s_incr <= '0';
s_IRQ_o <= '0';
when CHECK =>
s_incr <= '0';
s_IRQ_o <= '0';
when INCR =>
s_incr <= '1';
s_IRQ_o <= '0';
when IRQ =>
s_incr <= '0';
s_IRQ_o <= '1';
when WAIT_INT_ACK =>
s_incr <= '0';
s_IRQ_o <= '0';
when WAIT_RD =>
s_incr <= '0';
s_IRQ_o <= '0';
end case;
end process;
Int_Count_o <= std_logic_vector(s_count_int);
end Behavioral;
hdl/boards/svec/rtl/TOP_LEVEL.vhd 0 → 100644
View file @ 05346fed
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- Description:
-- The aim of this top level is to debug the vme64x interface so in the
-- WB side a RAM memory WB capable has been inserted as show in the following
-- block diagram.
--
-- TOP_LEVEL's block diagram
-- ____________________________________________________________
-- ___ | ______________________ ___________________ |
-- | B | | | | | | |
-- | A | | | VME TO WB | | | |
-- | C | | | INTERFACE | | | |
-- | K | | | (VME64xCore_Top.vhd) | | SPRAM | |
-- | P |_____|__| | |__________| WB | |
-- | L |_____|__| | |__________| SLAVE | |
-- | A | | | VME | WB |Point to | (xwb_ram.vhd) | |
-- | N | | | SLAVE | MASTER | Point | 64-bit port | |
-- | E | | | | |Interconn | Byte Granularity | |
-- | | | | | | | | |
-- | | | | | | | | |
-- |___| | |______________________| |___________________| |
-- |____________________________________________________________|
--
--
-- The wb slave supports the PIPELINED mode.
-- A little about the clk:
-- The VME is an asynchronous and handshake protocol so the vme64x interface
-- has to work at any clock frequency but since all the asynchronous signals
-- are sampled and the core work around the main FSM that of course is a synchronous
-- machine and the VME standards provide a set of timing rules, not all the
-- clock frequency ensure proper operation of the core.
--
-- 1) Fig. 25 pag. 107----"VMEbus Specification" ANSI/IEEE STD1014-1987
-- min 30ns
-- <------->
-- _________
-- AS*______/ \______
-- As show in the figure, to be sure that the slave detects the rising edge
-- and the following falling edge on the AS* signal the clk_i's period must be
-- maximum 30 ns.
-- 2) Fig. 20 pag. 99----"VMEbus Specification" ANSI/IEEE STD1014-1987
-- max 20ns
-- <--->
-- ______
-- \__________DSA*
-- ___________
-- \_____DSB*
-- The Master may not assert the data strobe lines at the same time; the
-- maximum delay between the two falling edge is 20 ns --> in the MFS
-- machine in the VME_bus.vhd file the LATCH_DS state has been inserted and the
-- minimum clk_i's period must be of 10 ns.
--
-- VME to WB interface:
-- See the VME64xCore_Top.vhd component
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
-- uncomment to use the PLL
Library UNISIM;
use UNISIM.vcomponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
entity TOP_LEVEL is
port(
clk_i : in std_logic;
Reset : in std_logic; -- hand reset; button PB1
-- VME
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_IACK_n_i : in std_logic;
-- VME buffers
VME_RETRY_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
end TOP_LEVEL;
architecture Behavioral of TOP_LEVEL is
COMPONENT VME64xCore_Top
PORT(
-- VME signals:
clk_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WB signals
DAT_i : in std_logic_vector(63 downto 0);
ERR_i : in std_logic;
RTY_i : in std_logic;
ACK_i : in std_logic;
STALL_i : in std_logic;
IRQ_i : in std_logic;
INT_ack : out std_logic;
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
WE_o : out std_logic;
reset_o : out std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT xwb_ram
generic(
g_size : natural := 256;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity
);
PORT(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
INT_ack : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
);
END COMPONENT;
signal WbDat_i : std_logic_vector(63 downto 0);
signal WbDat_o : std_logic_vector(63 downto 0);
signal WbAdr_o : std_logic_vector(63 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(7 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal Rst : std_logic;
signal clk_in_buf : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
signal s_INT_ack : std_logic;
signal s_rst : std_logic;
--mux
signal s_VME_DATA_b_o : std_logic_vector(31 downto 0);
signal s_VME_DATA_DIR : std_logic;
signal s_VME_ADDR_DIR : std_logic;
signal s_VME_ADDR_b_o : std_logic_vector(31 downto 1);
signal s_VME_LWORD_n_b_o : std_logic;
begin
Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
clk_i => clk_in,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => Rst,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b_i => VME_LWORD_n_b,
VME_LWORD_n_b_o => s_VME_LWORD_n_b_o,
VME_ADDR_b_i => VME_ADDR_b,
VME_ADDR_b_o => s_VME_ADDR_b_o,
VME_DATA_b_i => VME_DATA_b,
VME_DATA_b_o => s_VME_DATA_b_o,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => s_VME_DATA_DIR,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => s_VME_ADDR_DIR,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
DAT_i => WbDat_i,
DAT_o => WbDat_o,
ADR_o => WbAdr_o,
CYC_o => WbCyc_o,
ERR_i => WbErr_i,
RTY_i => WbRty_i,
SEL_o => WbSel_o,
STB_o => WbStb_o,
ACK_i => WbAck_i,
WE_o => WbWe_o,
STALL_i => WbStall_i,
IRQ_i => WbIrq_i,
INT_ack => s_INT_ack,
reset_o => s_rst,
-- Add by Davide for debug:
leds => leds
);
Inst_xwb_ram: xwb_ram
generic map(g_size => 256,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
)
port map(
clk_sys_i => clk_in,
rst_n_i => s_rst,
INT_ack => s_INT_ack,
slave1_i.cyc => WbCyc_o,
slave1_i.stb => WbStb_o,
slave1_i.adr => WbAdr_o,
slave1_i.sel => WbSel_o,
slave1_i.we => WbWe_o,
slave1_i.dat => WbDat_o,
slave1_o.ack => WbAck_i,
slave1_o.err => WbErr_i,
slave1_o.rty => WbRty_i,
slave1_o.stall => WbStall_i,
slave1_o.int => WbIrq_i,
slave1_o.dat => WbDat_i
);
Rst <= VME_RST_n_i and Reset;
---------------------------------------------------------------------------------
-- buffers...The buffers on the board work in the same way
VME_DATA_b <= s_VME_DATA_b_o when s_VME_DATA_DIR = '1' else (others => 'Z');
VME_ADDR_b <= s_VME_ADDR_b_o when s_VME_ADDR_DIR = '1' else (others => 'Z');
VME_LWORD_n_b <= s_VME_LWORD_n_b_o when s_VME_ADDR_DIR = '1' else 'Z';
---------------------------------------------------------------------------------
-- Outputs:
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
VME_DATA_DIR_o <= s_VME_DATA_DIR;
---------------------------------------------------------------------------------
-- uncomment to use the PLL:
PLL_BASE_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT clock outputs (1-64)
CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- (0.0-360.0).
CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
CLKOUT0_DIVIDE => 5,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- Duty cycle for CLKOUT# clock output (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
-- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
REF_JITTER => 0.016, -- Reference Clock Jitter in UI (0.000-0.999).
RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
)
port map (
CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
CLKOUT0 => clk_in_buf, --clk 80 MHz
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
CLKIN => clk_i, -- 1-bit input: Clock input
RST => '0' -- 1-bit input: Reset input
);
cmp_clk_dmtd_buf : BUFG
port map
(O => clk_in,
I => clk_in_buf);
-- comment the next line if the PLL is used:
-- clk_in <= clk_i;
end Behavioral;
hdl/boards/svec/rtl/genram_pkg.vhd 0 → 100644
View file @ 05346fed
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-05-11
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural ;
g_size : natural := 16 ;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
end genram_pkg;
hdl/boards/svec/rtl/ram_8bits.vhd 0 → 100644
View file @ 05346fed
--______________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________________
-- File: ram_8bits.vhd
--______________________________________________________________________________
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
entity ram_8bits is
generic (
size : natural := 256
);
Port ( addr : in std_logic_vector (f_log2_size(size)-1 downto 0);
di : in std_logic_vector (7 downto 0);
do : out std_logic_vector (7 downto 0);
we : in std_logic;
clk_i : in std_logic);
end ram_8bits;
architecture Behavioral of ram_8bits is
type t_ram_type is array(size-1 downto 0) of std_logic_vector(7 downto 0);
signal sram : t_ram_type;
begin
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (we = '1') then
sram(conv_integer(unsigned(addr))) <= di;
end if;
do <= sram(conv_integer(unsigned(addr)));
end if;
end process;
end Behavioral;
hdl/boards/svec/rtl/spram.vhd 0 → 100644
View file @ 05346fed
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: spram.vhd
--______________________________________________________________________________
-- Description: single port ram with byte granularity
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
entity spram is
generic (
-- standard parameters
g_data_width : natural := 64;
g_size : natural := 256;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := true; --not used
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "read_first"; -- not used
g_init_file : string := "" -- not used
);
port (
clk_i : in std_logic; -- clock input
-- byte write enable
bwe_i : in std_logic_vector(((g_data_width)/8)-1 downto 0);
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data input
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end spram;
architecture Behavioral of spram is
constant c_num_bytes : integer := (g_data_width)/8;
begin
spram: for i in 0 to c_num_bytes-1 generate
ram8bits : entity work.ram_8bits
generic map(g_size)
port map(addr => a_i,
di => d_i(8*i+7 downto 8*i),
do => q_o(8*i+7 downto 8*i),
we => bwe_i(i),
clk_i => clk_i
);
end generate;
end Behavioral;
hdl/boards/svec/rtl/wishbone_pkg.vhd 0 → 100755
View file @ 05346fed
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
package wishbone_pkg is
constant c_wishbone_address_width : integer := 64;
constant c_wishbone_data_width : integer := 64;
subtype t_wishbone_address is
std_logic_vector(c_wishbone_address_width-1 downto 0);
subtype t_wishbone_data is
std_logic_vector(c_wishbone_data_width-1 downto 0);
subtype t_wishbone_byte_select is
std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
subtype t_wishbone_cycle_type is
std_logic_vector(2 downto 0);
subtype t_wishbone_burst_type is
std_logic_vector(1 downto 0);
type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
type t_wishbone_address_granularity is (BYTE, WORD);
type t_wishbone_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wishbone_address;
sel : t_wishbone_byte_select;
we : std_logic;
dat : t_wishbone_data;
end record t_wishbone_master_out;
subtype t_wishbone_slave_in is t_wishbone_master_out;
type t_wishbone_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_slave_out;
subtype t_wishbone_master_in is t_wishbone_slave_out;
subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
type t_wishbone_address_array is array(integer range <>) of t_wishbone_address;
type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0):=
(others => 'X');
constant cc_dummy_data : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_slave_in : t_wishbone_slave_in :=
('X', 'X', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
constant cc_dummy_slave_out : t_wishbone_slave_out :=
('X', 'X', 'X', 'X', 'X', cc_dummy_data);
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_slave_adapter
generic (
g_master_use_struct : boolean;
g_master_mode : t_wishbone_interface_mode;
g_master_granularity : t_wishbone_address_granularity;
g_slave_use_struct : boolean;
g_slave_mode : t_wishbone_interface_mode;
g_slave_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := cc_dummy_sel;
sl_cyc_i : in std_logic := '0';
sl_stb_i : in std_logic := '0';
sl_we_i : in std_logic := '0';
sl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
sl_err_o : out std_logic;
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
ma_cyc_o : out std_logic;
ma_stb_o : out std_logic;
ma_we_o : out std_logic;
ma_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
ma_err_i : in std_logic := '0';
ma_rty_i : in std_logic := '0';
ma_ack_i : in std_logic := '0';
ma_stall_i : in std_logic := '0';
ma_int_i : in std_logic := '0';
master_i : in t_wishbone_master_in := cc_dummy_slave_out;
master_o : out t_wishbone_master_out);
end component;
component wb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
wb_adr_o : out std_logic_vector(c_wishbone_address_width - 1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_sel_o : out std_logic_vector(3 downto 0);
wb_cyc_o : out std_logic;
wb_dat_i : in std_logic_vector (c_wishbone_data_width-1 downto 0);
wb_ack_i : in std_logic;
wb_stall_i : in std_logic := '0');
end component;
component xwb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
component xwb_bus_fanout
generic (
g_num_outputs : natural;
g_bits_per_slave : integer;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_slave_interface_mode : t_wishbone_interface_mode := CLASSIC);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1));
end component;
component xwb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
cfg_address_i : in t_wishbone_address_array(g_num_slaves-1 downto 0);
cfg_mask_i : in t_wishbone_address_array(g_num_slaves-1 downto 0));
end component;
component xwb_dpram
generic (
g_size : natural;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave2_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave1_granularity : t_wishbone_address_granularity := WORD;
g_slave2_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end component;
component wb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component xwb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component wb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
scl_pad_i : in std_logic;
scl_pad_o : out std_logic;
scl_padoen_o : out std_logic;
sda_pad_i : in std_logic;
sda_pad_o : out std_logic;
sda_padoen_o : out std_logic);
end component;
component xwb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
scl_pad_i : in std_logic;
scl_pad_o : out std_logic;
scl_padoen_o : out std_logic;
sda_pad_i : in std_logic;
sda_pad_o : out std_logic;
sda_padoen_o : out std_logic);
end component;
component xwb_lm32
generic (
g_profile : string);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0);
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
iwb_o : out t_wishbone_master_out;
iwb_i : in t_wishbone_master_in);
end component;
component wb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "1.0";
g_ow_btp_overdrive : string := "5.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component xwb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "5.0";
g_ow_btp_overdrive : string := "1.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component wb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
pad_cs_o : out std_logic_vector(7 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component xwb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
pad_cs_o : out std_logic_vector(7 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component wb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component xwb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component wb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic);
end component;
component xwb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor);
end component;
component wb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
component xwb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
end wishbone_pkg;
hdl/boards/svec/rtl/xwb_ram.vhd 0 → 100755
View file @ 05346fed
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: xwb_ram.vhd
--______________________________________________________________________
-- Description: This block acts as WB Slave to test the vme64x interface
-- Block diagram:
-- ____________________________________________
-- | |
-- | |
-- | __________ ______________ |
-- | | WB | | INT_COUNT | |
-- | | LOGIC | |______________| |
-- W | | | ______________ |
-- B | | | | FREQ | |
-- | |__________| |______________| |
-- B | ______________ |
-- U | | | |
-- S | | | |
-- | | RAM | |
-- | ______________ | 64-bit port | |
-- | | | | Byte | |
-- | | IRQ | | Granularity | |
-- | | Generator | | | |
-- | | | | | |
-- | | | | | |
-- | | | |______________| |
-- | | | |
-- | |______________| |
-- |____________________________________________|
--
-- The RAM is a single port ram, 64 bit wide with byte granularity.
-- The INT_COUNT and FREQ registers are mapped in the location 0x00 of the
-- RAM memory, but these two 32 bit registers are outside the RAM because
-- they are used to generate the interrupt requests and some logic has been
-- added around these registers.
-- INT_COUNT --> address: 0x000
-- FREQ --> address: 0x004
-- The address above mentioned are the offsett VME address of the two registers
-- WB LOGIC: some process add to generate the acknowledge and stall signals.
-- IRQ Generator: this component sends an Interrupt request (pulse) to the
-- IRQ Controller --> Necessary to test the boards.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
entity xwb_ram is
generic(
g_size : natural := 256;
g_init_file : string := "";
g_must_have_init_file : boolean := false;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
INT_ack : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
);
end xwb_ram;
architecture struct of xwb_ram is
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
signal s_wea : std_logic;
signal s_bwea : std_logic_vector(c_wishbone_data_width/8-1 downto 0);
signal slave1_in : t_wishbone_slave_in;
signal slave1_out : t_wishbone_slave_out;
signal s_cyc : std_logic;
signal s_stb : std_logic;
COMPONENT IRQ_generator
PORT(
clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector(31 downto 0);
Int_Count_i : in std_logic_vector(31 downto 0);
Read_Int_Count : in std_logic;
INT_ack : in std_logic;
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector(31 downto 0)
);
END COMPONENT;
signal s_INT_COUNT : std_logic_vector(31 downto 0);
signal s_FREQ : std_logic_vector(31 downto 0);
signal s_q_o : std_logic_vector(63 downto 0);
signal s_q_o1 : std_logic_vector(63 downto 0);
signal s_en_Freq : std_logic;
signal s_sel_IntCount : std_logic;
signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_rst : std_logic;
signal s_stall : std_logic;
begin
-- reset
s_rst <= not(rst_n_i);
-- IRQ Generator, INT_COUNT and FREQ logic:
s_q_o1 <= s_INT_COUNT & s_FREQ;
s_en_Freq <= '1' when (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0
and s_bwea = "00001111") else '0';
s_Int_Count_o1 <= slave1_i.dat(63 downto 32) when (s_bwea = "11110000" and
(unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0)
else s_Int_Count_o;
s_Read_IntCount <= '1' when (slave1_i.we = '0' and slave1_i.sel = "11110000" and
(unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0 and
slave1_out.ack = '1') else '0';
-- Reg INT_COUNT
INT_COUNT : entity work.Reg32bit
port map(
reset => s_rst,
enable => '1',
di => s_Int_Count_o1,
do => s_INT_COUNT,
clk_i => clk_sys_i
);
-- Reg FREQ
FREQ : entity work.Reg32bit
port map(
reset => s_rst,
enable => s_en_Freq,
di => slave1_i.dat(31 downto 0),
do => s_FREQ,
clk_i => clk_sys_i
);
-- IRQ Generator
Inst_IRQ_generator: IRQ_generator PORT MAP(
clk_i => clk_sys_i,
reset => s_rst,
Freq => s_FREQ,
Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount,
INT_ack => INT_ack,
IRQ_o => slave1_o.int,
Int_Count_o => s_Int_Count_o
);
-- RAM memory
U_DPRAM : entity work.spram
generic map(
-- standard parameters
g_data_width => 64,
g_size => 256,
g_with_byte_enable => true,
g_init_file => "",
g_addr_conflict_resolution => "read_first"
)
port map(
clk_i => clk_sys_i,
bwe_i => s_bwea,
a_i => slave1_i.adr(f_log2_size(g_size)-1 downto 0),
d_i => slave1_i.dat,
q_o => s_q_o
);
-- WB Logic:
s_bwea <= slave1_i.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8);
s_wea <= slave1_i.we and slave1_i.cyc and slave1_i.stb and (not s_stall);
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(s_rst = '0') then
slave1_out.ack <= '0';
else
if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
slave1_out.ack <= '0';
else
slave1_out.ack <= slave1_i.cyc and slave1_i.stb and (not s_stall) ;
end if;
end if;
end if;
end process;
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(s_rst = '0') or slave1_out.ack = '1' then
s_stall <= '1';
elsif slave1_i.cyc = '1' then
s_stall <= '0';
end if;
end if;
end process;
slave1_o.dat <= s_q_o1 when unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0
else s_q_o;
slave1_o.stall <= s_stall;
slave1_o.err <= '0';
slave1_o.rty <= '0';
slave1_o.ack <= slave1_out.ack;
end struct;
hdl/boards/vfc/rtl/TOP_LEVEL.vhd
View file @ 05346fed
......@@ -64,7 +64,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -76,8 +77,8 @@
---------------------------------------------------------------------------------------
-- uncomment to use the PLL
-- Library UNISIM;
-- use UNISIM.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
......@@ -113,8 +114,6 @@ port(
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- not used
RST_i : in std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
......@@ -133,7 +132,6 @@ COMPONENT VME64xCore_Top
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic;
......@@ -154,7 +152,6 @@ COMPONENT VME64xCore_Top
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WB signals
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
ERR_i : in std_logic;
RTY_i : in std_logic;
......@@ -204,6 +201,7 @@ signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal Rst : std_logic;
signal clk_in_buf : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
......@@ -235,7 +233,6 @@ Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
VME_ADDR_b_o => s_VME_ADDR_b_o,
VME_DATA_b_i => VME_DATA_b,
VME_DATA_b_o => s_VME_DATA_b_o,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
......@@ -245,7 +242,6 @@ Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => s_VME_ADDR_DIR,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
RST_i => RST_i,
DAT_i => WbDat_i,
DAT_o => WbDat_o,
ADR_o => WbAdr_o,
......@@ -300,60 +296,64 @@ Inst_xwb_ram: xwb_ram
-- Outputs:
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
VME_DATA_DIR_o <= s_VME_DATA_DIR;
---------------------------------------------------------------------------------
-- uncomment to use the PLL:
-- PLL_BASE_inst : PLL_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
-- CLKFBOUT_MULT => 30, -- Multiply value for all CLKOUT clock outputs (1-64)
-- CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- -- (0.0-360.0).
-- CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- -- MHz).
-- -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
-- CLKOUT0_DIVIDE => 12,
-- CLKOUT1_DIVIDE => 1,
-- CLKOUT2_DIVIDE => 1,
-- CLKOUT3_DIVIDE => 1,
-- CLKOUT4_DIVIDE => 1,
-- CLKOUT5_DIVIDE => 1,
-- -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- -- Duty cycle for CLKOUT# clock output (0.01-0.99).
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKOUT3_DUTY_CYCLE => 0.500,
-- CLKOUT4_DUTY_CYCLE => 0.500,
-- CLKOUT5_DUTY_CYCLE => 0.500,
-- -- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- -- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT3_PHASE => 0.000,
-- CLKOUT4_PHASE => 0.000,
-- CLKOUT5_PHASE => 0.000,
-- CLK_FEEDBACK => "CLKFBOUT",
-- COMPENSATION => "SYSTEM_SYNCHRONOUS",
-- DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
-- REF_JITTER => 0.1, -- Reference Clock Jitter in UI (0.000-0.999).
-- RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
-- )
-- port map (
-- CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- -- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
-- CLKOUT0 => clk_in, --clk 50 MHz
-- CLKOUT1 => open,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
-- CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
-- CLKIN => clk_i, -- 1-bit input: Clock input
-- RST => '0' -- 1-bit input: Reset input
-- );
PLL_BASE_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT clock outputs (1-64)
CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- (0.0-360.0).
CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
CLKOUT0_DIVIDE => 5,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- Duty cycle for CLKOUT# clock output (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
-- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
REF_JITTER => 0.016, -- Reference Clock Jitter in UI (0.000-0.999).
RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
)
port map (
CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
CLKOUT0 => clk_in_buf, --clk 80 MHz
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
CLKIN => clk_i, -- 1-bit input: Clock input
RST => '0' -- 1-bit input: Reset input
);
cmp_clk_dmtd_buf : BUFG
port map
(O => clk_in,
I => clk_in_buf);
-- comment the next line if the PLL is used:
clk_in <= clk_i;
-- clk_in <= clk_i;
end Behavioral;
hdl/boards/vfc/rtl/ram_8bits.vhd
View file @ 05346fed
......@@ -13,7 +13,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......
hdl/boards/vfc/rtl/spram.vhd
View file @ 05346fed
......@@ -15,7 +15,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......
hdl/boards/vfc/sim/testbench/VME64x_Package.vhd
View file @ 05346fed
......@@ -40,7 +40,7 @@ package VME64x is
Vme64xADDR : Vme64xAddressType;
Vme64xDATA : Vme64xDataType;
--per ora nn gestisco IACKIN e BBSY
end record;
......@@ -144,6 +144,7 @@ constant ADER2_2e_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000
constant c_MBLT_Endian : std_logic_vector := x"7Ff53";
constant c_IRQ_Vector : std_logic_vector := x"7FF5F";
constant c_IRQ_level : std_logic_vector := x"7FF5B";
constant c_WB32or64 : std_logic_vector := x"7FF33";
-- CR constant
constant c_StartDefinedCR : std_logic_vector := x"00000";
constant c_EndDefinedCR : std_logic_vector := x"00FFF";
......
hdl/boards/vfc/sim/testbench/VME64x_TB.vhd
View file @ 05346fed
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/boards/vfc/syn/VME64xTest.xise
View file @ 05346fed
......@@ -197,7 +197,7 @@
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -325,7 +325,7 @@
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg676" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
......
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 05346fed
......@@ -8,8 +8,8 @@
-- Description:
-- This core implements an interface to transfer data between the VMEbus and the WBbus.
-- This core is a Slave in the VME side and Master in the WB side.
-- The main blocks: |
-- |
-- The main blocks:
--
-- ________________________________________________________________
-- | VME64xCore_Top.vhd |
-- |__ ____________________ __________________ |
......@@ -29,11 +29,22 @@
-- | | | | CR | | | |
-- | |____________________| |_______| |_________________| |
-- |________________________________________________________________|
--
-- All the VMEbus's asynchronous signals must be sampled 2 or 3 times to avoid |
-- metastability problem.
-- This core complies with the VME64x specifications and allows "plug and play"
-- configuration of VME crates.
-- The base address is setted by the Geographical lines.
-- The base address can't be setted by hand with the switches on the board.
-- If the core is used in an old VME system without GA lines, the core should be provided of
-- a logic that detects if GA = "11111" and if it is the base address of the module
-- should be derived from the switches on the board.
-- All the VMEbus's asynchronous signals must be sampled 2 or 3 times to avoid
-- metastability problem.
-- All the output signals on the WB bus are registered.
-- The Input signals from the WB bus aren't registered indeed the WB is a synchronous protocol and
-- some registers in the WB side will introduce a delay that make impossible reproduce the
-- WB PIPELINED protocol.
-- The WB Slave application must work at the same frequency of this vme64x core.
-- The main component is the VME_bus on the left of the block diagram. Inside this component
-- you can find the main finite state machine who coordinates all the synchronisms.
-- you can find the main finite state machine that coordinates all the synchronisms.
-- The WB protocol is more faster than the VME protocol so to make independent
-- the two protocols a FIFO memory can be introduced.
-- The FIFO is necessary only during 2eSST access mode.
......@@ -55,6 +66,7 @@
-- Access modes supported:
-- http://www.ohwr.org/projects/vme64x-core/repository/changes/trunk/
-- documentation/user_guides/VFC_access.pdf
-- This core is
--______________________________________________________________________________
--
-- References:
......@@ -69,7 +81,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -100,14 +113,12 @@
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
......@@ -119,9 +130,9 @@
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WishBone
RST_i : in std_logic;
VME_RETRY_OE_o : out std_logic;
-- WishBone
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
......@@ -172,7 +183,6 @@
signal s_INT_Vector : std_logic_vector(7 downto 0);
signal s_VME_IRQ_n_o : std_logic_vector(6 downto 0);
signal s_reset_IRQ : std_logic;
signal s_VME_GA_oversampled : std_logic_vector(5 downto 0);
signal s_CSRData_o : std_logic_vector(7 downto 0);
signal s_CSRData_i : std_logic_vector(7 downto 0);
signal s_CrCsrOffsetAddr : std_logic_vector(18 downto 0);
......@@ -335,7 +345,6 @@ begin
VME_DATA_DIR_o => s_VME_DATA_DIR_VMEbus,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_AM_i => VME_AM_oversampled,
VME_BBSY_n_i => VME_BBSY_n_i, -- not used
VME_IACK_n_i => VME_IACK_n_oversampled,
-- WB
memReq_o => STB_o,
......@@ -365,7 +374,6 @@ begin
CRAMwea_o => s_CRAMwea,
CRaddr_o => s_CRaddr,
CRdata_i => s_CRdata,
VME_GA_oversampled_o => s_VME_GA_oversampled,
en_wr_CSR => s_en_wr_CSR,
CrCsrOffsetAddr => s_CrCsrOffsetAddr,
CSRData_o => s_CSRData_o,
......@@ -426,7 +434,7 @@ begin
VME_DTACK_n_o => s_VME_DTACK_IRQ,
VME_DTACK_OE_o => s_VME_DTACK_OE_IRQ,
VME_DATA_o => s_VME_DATA_IRQ,
DataDir => s_VME_DATA_DIR_IRQ
VME_DATA_DIR_o => s_VME_DATA_DIR_IRQ
);
s_reset_IRQ <= not(s_reset);
......@@ -443,7 +451,7 @@ begin
CRAM_Wen => s_CRAMwea,
en_wr_CSR => s_en_wr_CSR,
CrCsrOffsetAddr => s_CrCsrOffsetAddr,
VME_GA_oversampled => s_VME_GA_oversampled,
VME_GA_oversampled => VME_GA_oversampled,
locDataIn => s_CSRData_o,
s_err_flag => s_err_flag,
s_reset_flag => s_reset_flag,
......
hdl/vme64x-core/rtl/VME_Access_Decode.vhd
View file @ 05346fed
......@@ -117,7 +117,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......
hdl/vme64x-core/rtl/VME_Am_Match.vhd
View file @ 05346fed
......@@ -25,7 +25,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 05346fed
......@@ -52,6 +52,8 @@
-- IRQ_level --> 0x7FF5B _|
--
-- MBLT_Endian --> 0x7FF53 --> for the swapper
--
-- WB32or64 --> 0x7FF33 --> if the bit 0 is '1' it means that the WB data bus is 32 bit
-- _
-- TIME0_ns --> 0x7FF4f |
-- TIME1_ns --> 0x7FF4b |
......@@ -60,7 +62,7 @@
-- TIME4_ns --> 0x7FF3f |
-- BYTES0 --> 0x7FF3b |
-- BYTES1 --> 0x7FF37 _|
--
--
-- CRAM memory Added. How to use the CRAM:
-- 1) The Master read the CRAM_OWNER Register location 0x7fff3; if 0 the CRAM is free
-- 2) The Master write his ID in the CRAM_OWNER Register location 0x7fff3
......@@ -98,7 +100,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -163,8 +166,19 @@ architecture Behavioral of VME_CR_CSR_Space is
signal s_CrCsrOffsetAddr : unsigned(18 downto 0);
signal s_locDataIn : unsigned(7 downto 0);
signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
signal s_odd_parity : std_logic;
signal s_BARerror : std_logic;
signal s_BAR_o : std_logic_vector(4 downto 0);
begin
-- check the parity:
s_odd_parity <= VME_GA_oversampled(5) xor VME_GA_oversampled(4) xor
VME_GA_oversampled(3) xor VME_GA_oversampled(2) xor
VME_GA_oversampled(1) xor VME_GA_oversampled(0);
-- If the crate is not driving the GA lines or the parity is odd the BAR register
-- is set to 0x00 and the following flag is asserted; the board will not answer if the
-- master accesses its CR/CSR space and we can see a time out error in the VME bus.
s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
--------------------------------------------------------------------------------
-- CR
process(clk_i)
......@@ -187,11 +201,13 @@ begin
for i in 254 downto WB32or64 loop -- Initialization of the CSR memory
s_CSRarray(i) <= c_csr_array(i);
end loop;
elsif s_bar_written = '0' then
elsif s_bar_written = '0' and s_odd_parity = '1' then
-- initialization of BAR reg to access the CR/CSR space
s_CSRarray(BAR)(7 downto 3) <= unsigned(not VME_GA_oversampled(4 downto 0));
s_CSRarray(BAR)(2 downto 0) <= "000";
s_bar_written <= '1';
s_bar_written <= '1';
elsif s_odd_parity = '0' then
s_CSRarray(BAR) <= (others => '0');
elsif (en_wr_CSR = '1') then
case to_integer(s_CrCsrOffsetAddr) is
when to_integer("00" & c_BAR_addr(18 downto 2)) =>
......@@ -350,8 +366,9 @@ begin
ModuleEnable <= s_CSRarray(BIT_SET_CLR_REG)(4);
MBLT_Endian_o <= std_logic_vector(s_CSRarray(MBLT_Endian)(2 downto 0));
Sw_Reset <= s_CSRarray(BIT_SET_CLR_REG)(7);
W32 <= s_CSRarray(WB32or64)(0);
BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3));
W32 <= s_CSRarray(WB32or64)(0);
BAR_o <= s_BAR_o;
s_BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3));
---------------------------------------------------------------------------------------------------------------
-- CRAM:
CRAM_1 : dpblockram
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ 05346fed
......@@ -7,7 +7,7 @@
--______________________________________________________________________________________
-- Description: ROM memory (CR space)
--______________________________________________________________________________
-- Authors: Erik Van der Bij (Erik.Van.der.Bij@cern.ch)
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
......@@ -15,6 +15,7 @@
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......
hdl/vme64x-core/rtl/VME_CSR_pack.vhd
View file @ 05346fed
......@@ -7,14 +7,15 @@
--________________________________________________________________________________________________
-- Description: This file defines the default configuration of the CSR space after power-up or software reset.
--______________________________________________________________________________
-- Authors: Erik Van der Bij (Erik.Van.der.Bij@cern.ch)
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -35,7 +36,7 @@ package VME_CSR_pack is
constant c_csr_array : t_CSRarray :=
(
BAR => x"00", --CR/CSR BAR
BIT_SET_CLR_REG => x"10", --Bit set register -- 0x10=module enable
BIT_SET_CLR_REG => x"00", --Bit set register -- 0x10=module enable
USR_BIT_SET_CLR_REG => x"00", --Bit clear register
CRAM_OWNER => x"00", --CRAM_OWNER
......@@ -77,7 +78,7 @@ FUNC6_ADER_3 =>x"00",
IRQ_Vector =>x"00", --"00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value
IRQ_level =>x"02",
WB32or64 =>x"00",
WB32or64 =>x"01", -- 32 bit WB of default
others => (others => '0'));
end VME_CSR_pack;
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 05346fed
......@@ -146,7 +146,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......
hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
View file @ 05346fed
......@@ -75,11 +75,12 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -111,7 +112,7 @@ entity VME_IRQ_Controller is
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector (31 downto 0);
DataDir : out std_logic);
VME_DATA_DIR_o : out std_logic);
end VME_IRQ_Controller;
architecture Behavioral of VME_IRQ_Controller is
......@@ -120,6 +121,7 @@ architecture Behavioral of VME_IRQ_Controller is
--output signals
signal s_DTACK : std_logic;
signal s_DTACK_OE : std_logic;
signal s_DTACK_OE_o : std_logic;
signal s_DataDir : std_logic;
signal s_IACKOUT : std_logic;
signal s_IACKOUT_o : std_logic;
......@@ -178,7 +180,7 @@ begin
DataDirOutputSample : FlipFlopD
port map(
sig_i => s_DataDir,
sig_o => DataDir,
sig_o => VME_DATA_DIR_o,
clk_i => clk_i,
reset => '0',
enable => '1'
......@@ -191,6 +193,14 @@ begin
reset => '0',
enable => '1'
);
DTACKOEOutputSample : FlipFlopD
port map(
sig_i => s_DTACK_OE,
sig_o => s_DTACK_OE_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
process(clk_i)
begin
......@@ -222,7 +232,7 @@ begin
end if;
end process;
-- Update next state
process(currs,INT_Req_sample,VME_AS_n_i,VME_DS_n_i,s_ack_int,VME_IACKIN_n_i)
process(currs,INT_Req_sample,VME_AS_n_i,VME_DS_n_i,s_ack_int,VME_IACKIN_n_i,AS_RisingEdge)
begin
case currs is
when IDLE =>
......@@ -295,7 +305,7 @@ begin
end process;
-- Update Outputs
process(currs,AS_RisingEdge)
process(currs,VME_AS1_n_i)
begin
case currs is
when IDLE =>
......@@ -447,7 +457,7 @@ begin
s_Data <= x"000000" & INT_Vector;
s_enable <= VME_IACKIN_n_i and s_IACKOUT_o;
-- the INT_Vector is in the D0:7 lines (byte3 in big endian order)
VME_DTACK_OE_o <= s_DTACK_OE;
VME_DTACK_OE_o <= s_DTACK_OE_o;
VME_IACKOUT_n_o <= s_IACKOUT_o;
end Behavioral;
......
hdl/vme64x-core/rtl/VME_Init.vhd
View file @ 05346fed
......@@ -13,7 +13,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......
hdl/vme64x-core/rtl/VME_SharedComps.vhd
View file @ 05346fed
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ 05346fed
......@@ -3,7 +3,7 @@
--
-- CERN,BE/CO-HT
--___________________________________________________________________________________
-- File: Wb_master.vhd
-- File: VME_Wb_master.vhd
--___________________________________________________________________________________
-- Description:
-- This component implements the WB master side in the vme64x core.
......@@ -246,13 +246,15 @@ begin
s_cardSel = '1' and s_sel = "11111111" and W32 = '0' else
(others => '0');
process(W32,s_rel_locAddr)
process(clk_i)
begin
if rising_edge(clk_i) then
if W32 = '0' then
locAddr_o <= b"000" & s_rel_locAddr(63 downto 3);
else
locAddr_o <= b"00" & s_rel_locAddr(63 downto 2);
end if;
end if;
end process;
err <= err_i;
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 05346fed
......@@ -66,7 +66,7 @@ use work.vme64x_pack.all;
entity VME_bus is
port(
clk_i : in std_logic;
reset_o : out std_logic;
reset_o : out std_logic; -- to the Interrupt Generator
-- VME signals
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
......@@ -89,7 +89,6 @@ entity VME_bus is
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic; -- not used
VME_IACK_n_i : in std_logic; -- USE VME_IACK_n_i and NOT VME_IACKIN_n_i !!!!
-- because VME_IACKIN_n_i is delayed the more you
-- are away from Slots 0
......@@ -105,21 +104,22 @@ entity VME_bus is
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
psize_o : out std_logic_vector(8 downto 0);
psize_o : out std_logic_vector(8 downto 0);
--FIFO Signals
VMEtoWB : out std_logic;
WBtoVME : out std_logic;
FifoMux : out std_logic;
transfer_done_i : in std_logic;
transfer_done_o : out std_logic;
--CR/CSR space signals:
CRAMaddr_o : out std_logic_vector(18 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMdata_i : in std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
CRaddr_o : out std_logic_vector(11 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
VME_GA_oversampled_o : out std_logic_vector(5 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
en_wr_CSR : out std_logic;
CrCsrOffsetAddr : out std_logic_vector(18 downto 0);
CSRData_o : out std_logic_vector(7 downto 0);
......@@ -257,7 +257,7 @@ architecture RTL of VME_bus is
-- Error signals
signal s_BERRcondition : std_logic; -- Condition for asserting BERR
signal s_wberr1 : std_logic;
signal s_rty1 : std_logic;
signal s_rty1 : std_logic;
-- Initialization signals
signal s_initInProgress : std_logic; --The initialization is in progress
signal s_initReadCounter : unsigned(8 downto 0); -- Counts read operations
......@@ -275,7 +275,7 @@ architecture RTL of VME_bus is
signal s_transfer_done_i : std_logic;
--
signal s_counter : unsigned(31 downto 0);
signal s_counter : unsigned(25 downto 0);
signal s_countcyc : unsigned(9 downto 0);
signal s_BERR_out : std_logic;
signal s_errorflag : std_logic;
......@@ -292,25 +292,24 @@ architecture RTL of VME_bus is
signal s_err : std_logic;
signal s_rty : std_logic;
-- transfer rate signals:
signal s_countertime : unsigned(19 downto 0);
signal s_countertime : unsigned(39 downto 0);
signal s_time : std_logic_vector(39 downto 0);
signal s_counterbytes : unsigned(8 downto 0);
signal s_bytes : std_logic_vector(12 downto 0);
signal s_time_ns : unsigned(39 downto 0);
signal s_counterbytes : unsigned(12 downto 0);
signal s_bytes : std_logic_vector(12 downto 0);
signal s_datawidth : unsigned(3 downto 0);
--
begin
--
s_FIFO <= '0'; -- FIFO not used if '0'
FifoMux <= s_FIFO;
---------
s_is_d64 <= '1' when s_sel= "11111111" else '0'; --for the VME_ADDR_DIR_o |
s_is_d64 <= '1' when s_sel= "11111111" else '0'; --used to drive the VME_ADDR_DIR_o
---------
s_RW <= VME_WRITE_n_i;
s_reset <= not(VME_RST_n_i) or s_sw_reset; -- hw and sw reset
reset_o <= s_reset; -- Asserted when high
VME_GA_oversampled_o <= VME_GA_i;
-- the GA lines are connected to the CR_CSR_Space to initialize the BAR |
-------------------------------------------------------------------------
-- These output signals are connected to the buffers on the board
-- SN74VMEH22501A Function table:
......@@ -490,6 +489,10 @@ begin
when IDLE =>
s_FSM <= c_FSM_default;
-- I don't need to drive the s_dtackOE, s_dataOE, s_addrOE, s_addrDir,
-- s_dataDir to 'Z' in the default configuration.
-- If the S_FPGA will be provided to a core who drives these lines without
-- erase the A_FPGA the above mentioned lines should be changed to 'Z' !!!
-- During the Interrupt ack cycle the Slave can't be accessed
-- so if VME_IACK is asserted the FSM is blocked in IDLE state.
-- The VME_IACK signal is asserted by the Interrupt handler
......@@ -506,12 +509,13 @@ begin
s_FSM.s_decode <= '1';
s_FSM.s_DSlatch <= '1';
-- uncomment for using 2e modes:
--if s_addressingType = TWOedge then -- start 2e transfer
-- s_mainFSMstate <= WAIT_FOR_DS_2e;
-- if s_addressingType = TWOedge then -- start 2e transfer
-- s_mainFSMstate <= WAIT_FOR_DS_2e;
if s_confAccess = '1' or (s_cardSel = '1') then
s_mainFSMstate <= WAIT_FOR_DS;
else
s_mainFSMstate <= DECODE_ACCESS;
-- another board will answer; wait here the rising edge on VME_AS_i
end if;
when WAIT_FOR_DS => -- wait until DS /= "11"
......@@ -531,7 +535,7 @@ begin
when LATCH_DS =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
......@@ -934,7 +938,7 @@ begin
end process;
-- BERR driver
-- The slave assert the Error line when during the Decode access phase an error
-- The slave assert the Error line if during the Decode access phase an error
-- condition is detected and the s_BERRcondition is asserted.
-- When the FSM is in the DTACK_LOW state one of the VME_DTACK and VME_BERR line is asserted.
-- The VME_BERR line can not be asserted by the slave at anytime, but only during
......@@ -996,9 +1000,9 @@ begin
end if;
end process;
--generate the error condition if block transfer overlap the limit
-- BLT --> block transfer limit = 256 bytes
-- MBLT --> block transfer limit = 2048 bytes
-- generate the error condition if block transfer overlap the limit
-- BLT --> block transfer limit = 256 bytes (rule 2.12a VME64 std ANSI/VITA 1-1994)
-- MBLT --> block transfer limit = 2048 bytes (rule 2.78 VME64 std ANSI/VITA 1-1994)
with s_transferType select
s_blockTransferLimit <= s_addrOffset(8) when BLT,
s_addrOffset(11) when MBLT,
......@@ -1226,10 +1230,11 @@ begin
end if;
end process;
--swap the data during read or write operation
--sel= 00 --> No swap
--sel= 01 --> Swap Byte eg: 01234567 became 10325476
--sel= 10 --> Swap Word eg: 01234567 became 23016745
--sel= 11 --> Swap Word+ Swap Byte eg: 01234567 became 32107654
--sel= 000 --> No swap
--sel= 001 --> Swap Byte eg: 01234567 became 10325476
--sel= 010 --> Swap Word eg: 01234567 became 23016745
--sel= 011 --> Swap Word+ Swap Byte eg: 01234567 became 32107654
--sel= 100 --> Swap DWord + Swap Word+ Swap Byte eg: 01234567 became 76543210
swapper_write: VME_swapper PORT MAP(
d_i => std_logic_vector(s_locDataIn),
sel => MBLT_Endian_i,
......@@ -1542,7 +1547,7 @@ end process;
if VME_RST_n_i = '0' or s_mainFSMreset = '1' then
s_countertime <= (others => '0');
elsif VME_AS_n_i = '0' then
s_countertime <= s_countertime + 1;
s_countertime <= s_countertime + unsigned(clk_period);
end if;
end if;
end process;
......@@ -1551,7 +1556,7 @@ end process;
begin
if rising_edge(clk_i) then
if s_mainFSMreset = '1' and s_cardSel = '1' then
s_time <= std_logic_vector(s_countertime * unsigned(clk_period));
s_time <= std_logic_vector(s_countertime);
end if;
end if;
end process;
......@@ -1562,7 +1567,7 @@ end process;
if VME_RST_n_i = '0' or s_mainFSMreset = '1' then
s_counterbytes <= (others => '0');
elsif s_memReq = '1' and s_cardSel = '1' then
s_counterbytes <= s_counterbytes + 1;
s_counterbytes <= s_counterbytes + s_datawidth;
end if;
end if;
end process;
......@@ -1571,7 +1576,7 @@ end process;
begin
if rising_edge(clk_i) then
if s_mainFSMreset = '1' and s_cardSel = '1' then
s_bytes <= std_logic_vector(unsigned(s_counterbytes * s_datawidth));
s_bytes <= std_logic_vector(unsigned(s_counterbytes));
end if;
end if;
end process;
......@@ -1694,7 +1699,7 @@ end process;
leds(4) <= s_led4;
-------------------------------------------------------------------------------------------
-- This process implements a simple 32 bit counter. If the bitstream file has been downloaded
-- This process implements a simple 26 bit counter. If the bitstream file has been downloaded
-- correctly and the clock is working properly you can see a led flash on the board.
process(clk_i)
begin
......
hdl/vme64x-core/rtl/VME_swapper.vhd
View file @ 05346fed
......@@ -17,7 +17,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 05346fed
......@@ -12,7 +12,8 @@
-- Version v0.01
--_______________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -61,7 +62,7 @@ package vme64x_pack is
-- Constants:
constant DFS : integer := 2; -- for accessing at the ADEM's bit 2
constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0
constant clk_period : std_logic_vector(19 downto 0) := "00000000000000110010";
constant clk_period : std_logic_vector(19 downto 0) := "00000000000000001101";
--AM table:
constant c_A24_S_sup : std_logic_vector(5 downto 0) := "111101";
constant c_A24_S : std_logic_vector(5 downto 0) := "111001";
......@@ -164,7 +165,7 @@ package vme64x_pack is
FUNC_XAMCAP => (add => 16#088#, len => 256),
FUNC_ADEM => (add => 16#188#, len => 32));
-- Main Finite State machine signals defoult:
-- Main Finite State machine signals default:
-- When the S_FPGA detects the magic sequency, it erases the A_FPGA so
-- I don't need to drive the s_dtackOE, s_dataOE, s_addrOE, s_addrDir, s_dataDir
-- to 'Z' in the default configuration.
......@@ -360,7 +361,6 @@ package vme64x_pack is
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_AM_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
memAckWB_i : in std_logic;
wbData_i : in std_logic_vector(63 downto 0);
......@@ -412,7 +412,6 @@ package vme64x_pack is
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
CRaddr_o : out std_logic_vector(11 downto 0);
VME_GA_oversampled_o : out std_logic_vector(5 downto 0);
en_wr_CSR : out std_logic;
CrCsrOffsetAddr : out std_logic_vector(18 downto 0);
CSRData_o : out std_logic_vector(7 downto 0);
......@@ -534,7 +533,7 @@ package vme64x_pack is
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
W32 : out std_logic;
W32 : out std_logic;
numBytes : in std_logic_vector(12 downto 0);
transfTime : in std_logic_vector(39 downto 0);
MBLT_Endian_o : out std_logic_vector(2 downto 0);
......@@ -546,37 +545,37 @@ package vme64x_pack is
COMPONENT VME_Am_Match
PORT(
clk_i : in std_logic;
s_reset : in std_logic;
s_mainFSMreset : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
DFS_i : in std_logic_vector(7 downto 0);
s_decode : in std_logic;
clk_i : in std_logic;
s_reset : in std_logic;
s_mainFSMreset : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
DFS_i : in std_logic_vector(7 downto 0);
s_decode : in std_logic;
AmMatch : out std_logic_vector(7 downto 0)
);
END COMPONENT;
......@@ -728,7 +727,7 @@ package vme64x_pack is
reset : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_AS1_n_i : in std_logic;
VME_AS1_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_LWORD_n_i : in std_logic;
VME_ADDR_123 : in std_logic_vector(2 downto 0);
......@@ -740,7 +739,7 @@ package vme64x_pack is
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector(31 downto 0);
DataDir : out std_logic
VME_DATA_DIR_o : out std_logic
);
END COMPONENT;
......
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