Commit 05346fed authored by dpedrett's avatar dpedrett

RST_i signal removed from VME64xCore_Top, add odd parity control, default…

RST_i signal removed from VME64xCore_Top, add odd parity control, default configuration: WB Data bus 32 bit, module disabled

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@151 665b4545-5c6b-4c24-801b-41150b02b44b
parent f4dd4cec
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-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-05-11
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural ;
g_size : natural := 16 ;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
end genram_pkg;
--______________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________________
-- File: ram_8bits.vhd
--______________________________________________________________________________
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
entity ram_8bits is
generic (
size : natural := 256
);
Port ( addr : in std_logic_vector (f_log2_size(size)-1 downto 0);
di : in std_logic_vector (7 downto 0);
do : out std_logic_vector (7 downto 0);
we : in std_logic;
clk_i : in std_logic);
end ram_8bits;
architecture Behavioral of ram_8bits is
type t_ram_type is array(size-1 downto 0) of std_logic_vector(7 downto 0);
signal sram : t_ram_type;
begin
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (we = '1') then
sram(conv_integer(unsigned(addr))) <= di;
end if;
do <= sram(conv_integer(unsigned(addr)));
end if;
end process;
end Behavioral;
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: spram.vhd
--______________________________________________________________________________
-- Description: single port ram with byte granularity
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
entity spram is
generic (
-- standard parameters
g_data_width : natural := 64;
g_size : natural := 256;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := true; --not used
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "read_first"; -- not used
g_init_file : string := "" -- not used
);
port (
clk_i : in std_logic; -- clock input
-- byte write enable
bwe_i : in std_logic_vector(((g_data_width)/8)-1 downto 0);
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data input
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end spram;
architecture Behavioral of spram is
constant c_num_bytes : integer := (g_data_width)/8;
begin
spram: for i in 0 to c_num_bytes-1 generate
ram8bits : entity work.ram_8bits
generic map(g_size)
port map(addr => a_i,
di => d_i(8*i+7 downto 8*i),
do => q_o(8*i+7 downto 8*i),
we => bwe_i(i),
clk_i => clk_i
);
end generate;
end Behavioral;
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--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: xwb_ram.vhd
--______________________________________________________________________
-- Description: This block acts as WB Slave to test the vme64x interface
-- Block diagram:
-- ____________________________________________
-- | |
-- | |
-- | __________ ______________ |
-- | | WB | | INT_COUNT | |
-- | | LOGIC | |______________| |
-- W | | | ______________ |
-- B | | | | FREQ | |
-- | |__________| |______________| |
-- B | ______________ |
-- U | | | |
-- S | | | |
-- | | RAM | |
-- | ______________ | 64-bit port | |
-- | | | | Byte | |
-- | | IRQ | | Granularity | |
-- | | Generator | | | |
-- | | | | | |
-- | | | | | |
-- | | | |______________| |
-- | | | |
-- | |______________| |
-- |____________________________________________|
--
-- The RAM is a single port ram, 64 bit wide with byte granularity.
-- The INT_COUNT and FREQ registers are mapped in the location 0x00 of the
-- RAM memory, but these two 32 bit registers are outside the RAM because
-- they are used to generate the interrupt requests and some logic has been
-- added around these registers.
-- INT_COUNT --> address: 0x000
-- FREQ --> address: 0x004
-- The address above mentioned are the offsett VME address of the two registers
-- WB LOGIC: some process add to generate the acknowledge and stall signals.
-- IRQ Generator: this component sends an Interrupt request (pulse) to the
-- IRQ Controller --> Necessary to test the boards.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
entity xwb_ram is
generic(
g_size : natural := 256;
g_init_file : string := "";
g_must_have_init_file : boolean := false;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
INT_ack : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
);
end xwb_ram;
architecture struct of xwb_ram is
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
signal s_wea : std_logic;
signal s_bwea : std_logic_vector(c_wishbone_data_width/8-1 downto 0);
signal slave1_in : t_wishbone_slave_in;
signal slave1_out : t_wishbone_slave_out;
signal s_cyc : std_logic;
signal s_stb : std_logic;
COMPONENT IRQ_generator
PORT(
clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector(31 downto 0);
Int_Count_i : in std_logic_vector(31 downto 0);
Read_Int_Count : in std_logic;
INT_ack : in std_logic;
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector(31 downto 0)
);
END COMPONENT;
signal s_INT_COUNT : std_logic_vector(31 downto 0);
signal s_FREQ : std_logic_vector(31 downto 0);
signal s_q_o : std_logic_vector(63 downto 0);
signal s_q_o1 : std_logic_vector(63 downto 0);
signal s_en_Freq : std_logic;
signal s_sel_IntCount : std_logic;
signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_rst : std_logic;
signal s_stall : std_logic;
begin
-- reset
s_rst <= not(rst_n_i);
-- IRQ Generator, INT_COUNT and FREQ logic:
s_q_o1 <= s_INT_COUNT & s_FREQ;
s_en_Freq <= '1' when (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0
and s_bwea = "00001111") else '0';
s_Int_Count_o1 <= slave1_i.dat(63 downto 32) when (s_bwea = "11110000" and
(unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0)
else s_Int_Count_o;
s_Read_IntCount <= '1' when (slave1_i.we = '0' and slave1_i.sel = "11110000" and
(unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0 and
slave1_out.ack = '1') else '0';
-- Reg INT_COUNT
INT_COUNT : entity work.Reg32bit
port map(
reset => s_rst,
enable => '1',
di => s_Int_Count_o1,
do => s_INT_COUNT,
clk_i => clk_sys_i
);
-- Reg FREQ
FREQ : entity work.Reg32bit
port map(
reset => s_rst,
enable => s_en_Freq,
di => slave1_i.dat(31 downto 0),
do => s_FREQ,
clk_i => clk_sys_i
);
-- IRQ Generator
Inst_IRQ_generator: IRQ_generator PORT MAP(
clk_i => clk_sys_i,
reset => s_rst,
Freq => s_FREQ,
Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount,
INT_ack => INT_ack,
IRQ_o => slave1_o.int,
Int_Count_o => s_Int_Count_o
);
-- RAM memory
U_DPRAM : entity work.spram
generic map(
-- standard parameters
g_data_width => 64,
g_size => 256,
g_with_byte_enable => true,
g_init_file => "",
g_addr_conflict_resolution => "read_first"
)
port map(
clk_i => clk_sys_i,
bwe_i => s_bwea,
a_i => slave1_i.adr(f_log2_size(g_size)-1 downto 0),
d_i => slave1_i.dat,
q_o => s_q_o
);
-- WB Logic:
s_bwea <= slave1_i.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8);
s_wea <= slave1_i.we and slave1_i.cyc and slave1_i.stb and (not s_stall);
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(s_rst = '0') then
slave1_out.ack <= '0';
else
if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
slave1_out.ack <= '0';
else
slave1_out.ack <= slave1_i.cyc and slave1_i.stb and (not s_stall) ;
end if;
end if;
end if;
end process;
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(s_rst = '0') or slave1_out.ack = '1' then
s_stall <= '1';
elsif slave1_i.cyc = '1' then
s_stall <= '0';
end if;
end if;
end process;
slave1_o.dat <= s_q_o1 when unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0
else s_q_o;
slave1_o.stall <= s_stall;
slave1_o.err <= '0';
slave1_o.rty <= '0';
slave1_o.ack <= slave1_out.ack;
end struct;
......@@ -64,7 +64,8 @@
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
......@@ -76,8 +77,8 @@
---------------------------------------------------------------------------------------
-- uncomment to use the PLL
-- Library UNISIM;
-- use UNISIM.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
......@@ -113,8 +114,6 @@ port(
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- not used
RST_i : in std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
......@@ -133,7 +132,6 @@ COMPONENT VME64xCore_Top
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic;
......@@ -154,7 +152,6 @@ COMPONENT VME64xCore_Top
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WB signals
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
ERR_i : in std_logic;
RTY_i : in std_logic;
......@@ -204,6 +201,7 @@ signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal Rst : std_logic;
signal clk_in_buf : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
......@@ -235,7 +233,6 @@ Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
VME_ADDR_b_o => s_VME_ADDR_b_o,
VME_DATA_b_i => VME_DATA_b,
VME_DATA_b_o => s_VME_DATA_b_o,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
......@@ -245,7 +242,6 @@ Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => s_VME_ADDR_DIR,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
RST_i => RST_i,
DAT_i => WbDat_i,
DAT_o => WbDat_o,
ADR_o => WbAdr_o,
......@@ -300,60 +296,64 @@ Inst_xwb_ram: xwb_ram
-- Outputs:
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
VME_DATA_DIR_o <= s_VME_DATA_DIR;
---------------------------------------------------------------------------------
-- uncomment to use the PLL:
-- PLL_BASE_inst : PLL_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
-- CLKFBOUT_MULT => 30, -- Multiply value for all CLKOUT clock outputs (1-64)
-- CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- -- (0.0-360.0).
-- CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- -- MHz).
-- -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
-- CLKOUT0_DIVIDE => 12,
-- CLKOUT1_DIVIDE => 1,
-- CLKOUT2_DIVIDE => 1,
-- CLKOUT3_DIVIDE => 1,
-- CLKOUT4_DIVIDE => 1,
-- CLKOUT5_DIVIDE => 1,
-- -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- -- Duty cycle for CLKOUT# clock output (0.01-0.99).
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKOUT3_DUTY_CYCLE => 0.500,
-- CLKOUT4_DUTY_CYCLE => 0.500,
-- CLKOUT5_DUTY_CYCLE => 0.500,
-- -- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- -- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT3_PHASE => 0.000,
-- CLKOUT4_PHASE => 0.000,
-- CLKOUT5_PHASE => 0.000,
-- CLK_FEEDBACK => "CLKFBOUT",
-- COMPENSATION => "SYSTEM_SYNCHRONOUS",
-- DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
-- REF_JITTER => 0.1, -- Reference Clock Jitter in UI (0.000-0.999).
-- RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
-- )
-- port map (
-- CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- -- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
-- CLKOUT0 => clk_in, --clk 50 MHz
-- CLKOUT1 => open,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
-- CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
-- CLKIN => clk_i, -- 1-bit input: Clock input
-- RST => '0' -- 1-bit input: Reset input
-- );
PLL_BASE_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT clock outputs (1-64)
CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- (0.0-360.0).
CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
CLKOUT0_DIVIDE => 5,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- Duty cycle for CLKOUT# clock output (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
-- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,