Commit 02a397d1 authored by Sebastian Owarzany's avatar Sebastian Owarzany

hdl/rtl/xvme64x_core.vhd | hdl/rtl/vme64x_core_verilog.vhd add default return for functions

parent fbd7dbbf
...@@ -131,7 +131,9 @@ entity vme64x_core_verilog is ...@@ -131,7 +131,9 @@ entity vme64x_core_verilog is
if X = "BYTE" then if X = "BYTE" then
return BYTE ; return BYTE ;
end if; end if;
return BYTE ;
end string_to_wb_grn ; end string_to_wb_grn ;
function string_to_wb_mode(X : string) function string_to_wb_mode(X : string)
return t_wishbone_interface_mode is return t_wishbone_interface_mode is
begin begin
...@@ -141,6 +143,7 @@ entity vme64x_core_verilog is ...@@ -141,6 +143,7 @@ entity vme64x_core_verilog is
if X = "PIPELINED" then if X = "PIPELINED" then
return PIPELINED ; return PIPELINED ;
end if; end if;
return PIPELINED ;
end string_to_wb_mode ; end string_to_wb_mode ;
end vme64x_core_verilog; end vme64x_core_verilog;
......
...@@ -120,7 +120,6 @@ entity xvme64x_core is ...@@ -120,7 +120,6 @@ entity xvme64x_core is
g_END_SN : std_logic_vector(23 downto 0) := x"000000"; g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_USE_CUSTOM_ADER : Boolean := false; g_USE_CUSTOM_ADER : Boolean := false;
-- Function decoder parameters. -- Function decoder parameters.
g_DECODER : t_vme64x_decoder_arr := c_vme64x_decoders_default); g_DECODER : t_vme64x_decoder_arr := c_vme64x_decoders_default);
port ( port (
...@@ -192,6 +191,7 @@ architecture rtl of xvme64x_core is ...@@ -192,6 +191,7 @@ architecture rtl of xvme64x_core is
return i; return i;
end if; end if;
end loop; end loop;
return 0;
end least_set_bit; end least_set_bit;
-- Compute the ADER for each function if CR/CSR is not used. For example: -- Compute the ADER for each function if CR/CSR is not used. For example:
......
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