VME64xCore_Top Project Status (01/20/2011 - 10:13:31)
Project File: VME64e_ISE.xise Parser Errors: No Errors
Module Name: VME64xCore_Top Implementation State: Mapped (Failed)
Target Device: xc6slx45t-3fgg484
  • Errors:
 
Product Version:ISE 12.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 1534 54576 2%
Number of Slice LUTs 3060 27288 11%
Number of fully used LUT-FF pairs 1007 3587 28%
Number of bonded IOBs 310 296 104%
Number of Block RAM/FIFO 4 116 3%
Number of BUFG/BUFGCTRLs 1 16 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jan 19 19:12:32 2011   
Translation ReportCurrentWed Jan 19 19:12:38 2011   
Map ReportOut of DateTue Jan 18 16:49:33 2011   
Place and Route Report     
Power Report     
Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 01/20/2011 - 11:48:36