VME64xCore_Top Project Status (01/20/2011 - 10:13:31) | |||
Project File: | VME64e_ISE.xise | Parser Errors: | No Errors |
Module Name: | VME64xCore_Top | Implementation State: | Mapped (Failed) |
Target Device: | xc6slx45t-3fgg484 |
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Product Version: | ISE 12.4 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 1534 | 54576 | 2% | |
Number of Slice LUTs | 3060 | 27288 | 11% | |
Number of fully used LUT-FF pairs | 1007 | 3587 | 28% | |
Number of bonded IOBs | 310 | 296 | 104% | |
Number of Block RAM/FIFO | 4 | 116 | 3% | |
Number of BUFG/BUFGCTRLs | 1 | 16 | 6% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed Jan 19 19:12:32 2011 | ||||
Translation Report | Current | Wed Jan 19 19:12:38 2011 | ||||
Map Report | Out of Date | Tue Jan 18 16:49:33 2011 | ||||
Place and Route Report | ||||||
Power Report | ||||||
Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |