Tristan Gingold (a6458036) at 30 Nov 12:47
Merge branch 'patch-3' into 'master'
... and 1 more commit
Add some missing reset values, so the signals propagated to the WB are not 'X' when the simulation starts. No impact on the functionality.
Add some missing reset values, so the signals propagated to the WB are not 'X' when the simulation starts. No impact on the functionality.
Dimitris Lampridis (f50d79fc) at 26 May 06:59
Add g_ASYNC_DTACK to verilog wrapper
Dimitris Lampridis (f50d79fc) at 26 May 06:59
Dimitris Lampridis (a0ca042e) at 26 May 06:54
Closes #28
Tristan Gingold (869fe405) at 25 May 13:03
Merge branch 'add_g_async_dtack_to_verilog' into 'master'
... and 1 more commit
Tom Levens (f50d79fc) at 25 May 12:32
Add g_ASYNC_DTACK to verilog wrapper
Closes #28
Tom Levens (a0ca042e) at 25 May 12:23
Sebastian Owarzany (02a397d1) at 20 Dec 16:13
hdl/rtl/xvme64x_core.vhd | hdl/rtl/vme64x_core_verilog.vhd add defa...
Sebastian Owarzany (fbd7dbbf) at 16 Dec 13:19
hdl/sim/vme64x_bfm/components/sn74vmeh22501.v add explicitly netttypes
... and 8 more commits
Dimitris Lampridis (601b259c) at 03 Nov 07:49
xvme64x_core.vhd: workaround vivado 2020 bug.
Dimitris Lampridis (a0ca042e) at 03 Nov 07:49
Thanks!
Tom Levens (ad348ef4) at 19 Oct 07:21