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VME ADC 250k 16b 36cha
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Last edited by OHWR Gitlab support Mar 15, 2019
Page history

VME ADC 250k 16b 36cha

Project description

The 250 kHz, 36 channel, simultaneous sampling, ADC card is intended to be used for
SEMGrids and other applications where tens or hundreds of simultaneously sampled channels are
needed. Many other applications like wire scanner readout of Faraday Cup acquisition are
possible. The card is equipped with both VME32 and serial interfaces, so it can be used outside
the VME crate.
The card is organized as 6 ADC units, 6 channels each. The total number of independent
ADCs is therefore 36. The sampling clock for the ADCs can be delivered externally, or generated
inside the card. This enables cascading and synchronization of many cards. The sampling clock
frequency can be adjusted using one of the card registers. The card has three trigger sources – 2
external hardware signals and one controlled by software.



VME ADC production board*


Functional specifications

  • Number of channels: 36 with flat cable input
  • Resolution: 16 bits
  • Max sampling rate 250kS/s per Channel, simultaneous sampling of all 36 channels
  • Inputs Differential, Instrumentation amplifier at each input
  • Input range Selectable (/-5V,/- 10V), adjustable gain(resistor)
  • Input protection up to +/-100V
  • Interfaces: VME 6U, 32bit DATA, 24 bit ADDR, RS232, RS485
  • Programmable logic FPGA, 8,000 Logic Cells, CPLD 570LC
  • Memory SDRAM 64MB, max 128MB (option)
  • Digital I/O:
    • 2x trigger input (TTL)
    • 3x general I/O (TTL)
    • RS232C
    • RS485
  • Indicators: 9 LEDs at the front panel
  • Card identification
    • 48 bit unique serial number, 8 bit Address switch (address bits 23:16)
    • FPGA version register
    • CPLD version register
  • FPGA remote programming/configuration
  • Internal voltage monitoring
  • Input signal connectors: IDC, compatible with MPV901

Detailed project information

  • Documentation:
    • Schematics (PDF, Altium sources)
    • PCB (PDF, Altium source)
  • Users
  • User manual.
  • Example test report.

Project status

Date Event
2007-2009 Main features specification written, PCB designed and 50 pieces of PCB v1 produced and tested
5-06-2013 Preliminary version of v2 schematics done. Project undergoes serious mechanical modifications to improve reliability.
7-06-2013 HDL compilation for new schematics is done. SW and HDL compatibility is ensured.
15-06-2013 Initial component placement for v2 - flex PCB, lack of problematic FPC jumpers.
16-06-2013 Mechanical design of shield and panels done
10-07-2013 3 prototype devices were produced and delivered
15-07-2013 Construction of production test suite succeeded, boards after cosmetic changws ready for mass production
10-08-2013 140 PCBs delivered, including 3 assembled for tests
19-08-2013 3 pieces pass PTS tests and assembly of rest of the boards started

Filip Świtakowski - 18 Aug 2014

Files

  • VME_ADC36.jpg
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