VME FMC Carrier HPC-DDR3
Project description
The VFC-HD is an Altera based VME64x carrier for one High Pin Count (HPC) FPGA Mezzanine Card (FMC, VITA 57). It has six SFP+ transceivers compatible with rad-hard GBT links, CERN Beam Synchronous Timing (BST), White Rabbit and Ethernet. A single DDR3 SODIMM slot allows the use of off-the-shelf memory modules.
The card has been developed by the Beam Instrumentation (BI) group at CERN as a general purpose digital acquisition card. It replaces the VFC which is no longer under development by BI.
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VFC-HPC V1.0* (development version with SRAM)
Main Features
- Altera Arria V GX FPGA (5AGXMB1G4F40C4N)
- HPC FMC slot
- Fully populated LA, HA & HB banks
- 10 gigabit lanes connected to FPGA transceivers
- Programmable Vadj
- 6 SFP+ running up to 6.5Gbps
- 4 "application" for GBT connections
- 2 "system" for BST/White Rabbit/ethernet
- 40 single ended (or 20 LVDS) connections to VME P2 available for rear transition modules
- 30 single ended connections to VME64x P0 to support clock & trigger distribution in (custom) BI LHC VME crates
- Flexible clocking resources
- Si570 10-280MHz programmable oscillator
- CDR for Beam Synchronous Timing (BST) reception
- Standard VCXOs for White Rabbit support
- Si5338 clock synthesizer
- DDR3 slot supporting up to 8GB SODIMMs
- Front panel connectivity:
- 6 SFP+ cages
- 4 LEMO-00 general purpose I/O
- 8 user LEDs
- 12 layer PCB
Project information
- Official design data EDMS EDA-XXXXX
- LHC equipment name: XXXXX
- Schematic diagram: xxx
- Overview presentation: xxx
- Bill of material: xxx
- Manufacturing test suite
Users
Contact
- Andrea Boccardi - CERN
Status
Date | Event |
09-02-2015 | Inclusion of project on OHWR |
Tom Levens - 09 February 2015