VME FMC Carrier HPC-DDR3
Main Features
- Altera Arria V GX FPGA (5AGXMB1G4F40C4N)
- HPC (High Pin Count) FMC slot
- 40 single ended (20 LVDS) connections to VME P2 available for rear transition modules
- Flexible clocking resources
- Si570 10-280MHz programmable oscillator
- CDR for Beam Synchronous Timing (BST) reception
- Standard VCXOs for White Rabbit support
- Si5338 clock synthesizer
- DDR3 slot supporting up to 8GB SODIMMs
- Front panel connectivity:
- 6 SFP+ transceivers
- 4 LEMO GPIO
- 8 LEDs
Documentation
Technical specifications
- Official design data EDMS EDA-XXXXX
- LHC equipment name: XXXXX
- Schematic diagram: xxx
- Overview presentation: xxx
- Bill of material: xxx
- Manufacturing test suite
Users
Status
Date | Event |
09-02-2015 | Start of project on OHWR |
Tom Levens - 09 February 2015