Getting Started with WRNC VHDL
In order to speed up your VHDL design process, we provided a simple WR Node template design for the SVEC carrier. A SPEC version will be coming soon.
The template (marked pink on the diagram below) contains a complete WR node environment:
- the WR Node core with two CPUs and user-configurable number of queues
- full White Rabbit stack (with Etherbone)
- a VME 64x core.
The template VHDL design (svec_node_template
) is located in the WRNC
gateware Git
repository
We additionally provided an example top level application, which allows
the node CPUs to control the 4 LEMO connectors and 8 bi-color LEDs on
the SVEC's front panel. The design simply connects two concurrent GPIO
ports to the CPUs and some tri-state buffers (see diagram above). The
ISE project
is located
here
The WR Node software project provides full documentation on as well as a quick guide for installing and deploying the Node's real time software.