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Dimitris Lampridis authored
It causes errors in newer versions (3+) of hdlmake, when the targer is FPGA synthesis and it is not needed since the folder is also included by higher level Manifests for simulation testbenches.
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ip_cores | ||
rtl | ||
sw | ||
syn/spec | ||
tb | ||
top/spec | ||
.gitmodules | ||
Manifest.py |