urv-core issueshttps://ohwr.org/project/urv-core/issues2024-02-16T13:55:03Zhttps://ohwr.org/project/urv-core/issues/8Bug: register x0 should be hardwired to zero2024-02-16T13:55:03ZShareef JalloqBug: register x0 should be hardwired to zeroWhile running the Riscof test suite I ended up chasing a bug caused by the RAM implementation of the register file allowing writes to `x0`. Reads to this address should just return 0.Tristan GingoldTristan Gingoldhttps://ohwr.org/project/urv-core/issues/5Use Verible for Verilog formatting2024-02-14T13:43:04ZShareef JalloqUse Verible for Verilog formattingMuch of the Verilog formatting seems to be broken. It could just be the difference between using tabs/spaces but some of it is hard to read.
I'd suggest using a tool such as the Verible Verilog formatter, `verible-verilog-format`. I use this along with some other whitespace fixers inside of `pre-commit` which might make it easy to integrate.
Just thought I'd start a conversation to discuss before starting any work.
If you haven't come across these tools before:
https://pre-commit.com/
https://github.com/chipsalliance/verible/blob/master/verilog/tools/formatter/README.mdhttps://ohwr.org/project/urv-core/issues/4Linting issues2024-02-12T10:10:51ZShareef JalloqLinting issuesHi,
I've been running Verilator in its linting mode and there are quite a few errors that need to be fixed. I've made the easy fixes but there are a few that need clarification.
You can see the simple fixes here: https://github.com/NuQuantum/urv-core/commit/87531fca8366dfae91d35f01b6517ec029e6ee81
For the ones that need input, they are all currently waived in this [waiver file.](https://github.com/NuQuantum/urv-core/blob/fusesoc/lint/cpu_core.vlt#L3)
There are some width mismatches in the multiplier that I could work out the intent for:
```
ERROR: %Warning-WIDTHEXPAND: src/ohwr_urv_cpu_core_0/rtl/urv_multiply.v:258:32: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'yl_xl' generates 36 bits.
: ... In instance urv_cpu.execute.genblk1.multiplier
258 | wire [63:0] yl_xl_ext = yl_xl;
| ^
... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.014
... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message.
%Warning-WIDTHTRUNC: src/ohwr_urv_cpu_core_0/rtl/urv_multiply.v:259:32: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's REPLICATE generates 68 bits.
: ... In instance urv_cpu.execute.genblk1.multiplier
259 | wire [63:0] yh_xl_ext = { {15{yh_xl[35] } }, yh_xl, 17'h0 };
| ^
%Warning-WIDTHTRUNC: src/ohwr_urv_cpu_core_0/rtl/urv_multiply.v:260:32: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's REPLICATE generates 68 bits.
: ... In instance urv_cpu.execute.genblk1.multiplier
260 | wire [63:0] yl_xh_ext = { {15{yl_xh[35] } }, yl_xh, 17'h0 };
| ^
%Warning-WIDTHTRUNC: src/ohwr_urv_cpu_core_0/rtl/urv_multiply.v:261:32: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's REPLICATE generates 70 bits.
: ... In instance urv_cpu.execute.genblk1.multiplier
261 | wire [63:0] yh_xh_ext = { xh_yh, 34'h0 };
| ^
%Error: Exiting due to 4 warning(s)
make: *** [Makefile:23: lint-only] Error 1
ERROR: Failed to build ohwr:urv:cpu_core:0 : '['make', 'lint-only']' exited with an error: 2
```
Then there are a bunch of other errors that need to be fixed that include:
* Missing generate block names
* Incomplete case statements that probably just require unused states to be defined.
* module names not match file names
* the use of non-blocking statements in combinational always blocks
I'm happy to help sort these out and issue a pull request if you can help with the width mismatches.
Shareef.