urv-core:9016844b52592856d58bd54bcf57d07c0c3c0f1f commitshttps://ohwr.org/project/urv-core/commits/9016844b52592856d58bd54bcf57d07c0c3c0f1f2018-03-11T19:13:23Zhttps://ohwr.org/project/urv-core/commit/9016844b52592856d58bd54bcf57d07c0c3c0f1fcore: fixed incorrect exception handling (exception address delayed by 1 ins...2018-03-11T19:13:23ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/f1fcd338aefb276b89c502c7c52d6e7b26cebdfeSilence Xilinx unisim warnings at 0ps during simulations regarding invalid OP...2018-03-09T16:47:55ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/urv-core/commit/e03cb487987b51ab7ced80648d469a0326b7e542Remove include_dirs from rtl Manifest.2018-03-09T09:43:07ZDimitris LampridisDimitris.Lampridis@cern.ch
It causes errors in newer versions (3+) of hdlmake, when the targer is FPGA synthesis and it is not
needed since the folder is also included by higher level Manifests for simulation testbenches.https://ohwr.org/project/urv-core/commit/c5e4a77d38fad6e2037c54426f2792263d93ab64Add top-level Manifest.py for easier inclusion as git submodule in other proj...2018-03-05T15:39:51ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/urv-core/commit/6f77e1e8268e186b45d86de811a9758a0c1bf3b7core: fixed missing interrupts/exceptions bug2017-11-12T21:26:33ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/bc0aef8ae10183c8de307952f39979bf48f1a27afix a typo2016-12-14T10:25:58ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/248e8d0980a3ce1e8b9575408550cce254bc46a8rtl: updated manifest & copyright notice2015-12-09T14:12:40ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/ab368881d083ecf60097ee3cb7de9fa7bba2f6d8rtl: support for 32K IRAM on Spartan62015-12-09T14:12:20ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/ded499857af9cebdff1ab29e7131f6d71fabbc69updated copyright notice2015-10-09T11:29:34ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/2c1d6de5ebed8ee990131df24132a7bb207002cartl: various fixes2015-10-08T13:56:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/1e31766426d302d7f4f62e6f5017948655b9b95curv_regfile: don't bypass when stalled.2015-10-08T13:56:24ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/c5807b5879dfcb7b35122fa70243e756c53fb6c4coremark & ISA testsuite TB2015-09-29T17:58:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/1cf413e9e85511a3d824809e22d6557f18edfb01added top level for the SPEC & some missing files2015-09-29T17:40:05ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/014209e9c2e33c5fbdf5f40529237be36667fcf1code cleanup & relicensing2015-09-25T12:17:39ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/695e846777a9a0764f65e2cd4f8e84a28fe34985wip2015-09-22T13:59:34ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/d36aadc821d9e064dd5c0e5410d2142218e6e1f1rtl: some area optimizations2015-09-09T11:43:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/b9db49397d3cb1ed4876ee85e93e15635dcc3078wip2015-09-01T22:51:50ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/660ec75191f7d39ca5fe681184f86c6d390f7991100 MHz version, still room for improvement2015-09-01T18:25:20ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/51d4addc2119fe16ddddf364ba7a015f48dfc7c8optimizing bypass...2015-08-31T22:16:04ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/de6bfd7b544e0ed09be7c79bb21efbdc5c5709c8test suite running2015-08-24T10:06:53ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/4ad34ecaccef9cea4a58bc527181b3005e1a74eartl: passes RV32IM test suite2015-08-24T10:03:23ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/7630ec3a3c4e79ab3bd375a539b437ff1fb5284eadded multiply2015-08-13T21:42:03ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/24a3f937bdf5ee4b1d8b187ab0e93ab8e9bb1024we run coremark!2015-08-13T17:48:18ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/b25e4d388c52a13a5618fc531263b0a1043c16aewip2015-08-12T11:18:43ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/7dc634dccbcfa3428d72b03ac533a5f1ff66a566working on exceptions2015-08-10T14:16:32ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/b57333c6522d7284743bd9bb9b24aa2731cbd673top level @ SPEC card working!2015-05-28T08:40:52ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/3a06e0073bc462e350aafde45c78e1d6edb2f01eadded hello world & UART bootloader2015-05-28T08:40:16ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/8680d785b5dce7dfabaadca4655c93578b7a479bfixed WB stall2015-05-28T08:37:48ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/40e55b9a00c90a9ed88911130b61ec0802641999moved files around, added test sw2015-05-27T17:52:09ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/fa287419fb995fbbdd3c70e440e66fbe1e9902adadded barrel shifteR2015-05-27T17:49:56ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/874f587a99e11bbc6bf581069056c40ed9b3aee7wip on wishbone BIU2015-05-27T17:49:31ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/14e06a774ea72b55d998570e055cf1a54644b847fixed wait states on long reads/writes2015-05-27T17:38:59ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/b2bc141b4335dcce782eb11c9a0f6f83fedc0763shifter refactor2015-05-26T23:51:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/1cc11f80441b449fa09865bb494c57e4a38e2990fixed dropped jump if followed by multicycle instruction2015-05-26T18:10:13ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/a9fae1acb821e0c66346e0b1af26a7866355cd9esimplify mem address generation2015-05-26T16:30:05ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/18f2be7274db1e0c3cb88b42e911832285acb575attempt to pipeline decoding even more2015-05-26T16:12:31ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/15333cd69002cdda5212b3da58879b8c2d9ba2abremoved ugly mem2mem bypass2015-05-26T15:41:01ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/c374e8af62653a29d0ed47ff7c205bc72004682a4-stage pipeline running sorting test program2015-05-26T15:22:10ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/08a9b8d4ab382b846583377909a1dd7c49b4f9efload interlock seems to work2015-05-26T00:50:11ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/2512ebf0702a53b5b50ca1454107ddc099842033will add D stage2015-05-25T22:32:59ZTomasz Włostowskitomasz.wlostowski@cern.ch