urv-core:4ad34ecaccef9cea4a58bc527181b3005e1a74ea commitshttps://ohwr.org/project/urv-core/commits/4ad34ecaccef9cea4a58bc527181b3005e1a74ea2015-08-24T10:03:23Zhttps://ohwr.org/project/urv-core/commit/4ad34ecaccef9cea4a58bc527181b3005e1a74eartl: passes RV32IM test suite2015-08-24T10:03:23ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/7630ec3a3c4e79ab3bd375a539b437ff1fb5284eadded multiply2015-08-13T21:42:03ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/24a3f937bdf5ee4b1d8b187ab0e93ab8e9bb1024we run coremark!2015-08-13T17:48:18ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/b25e4d388c52a13a5618fc531263b0a1043c16aewip2015-08-12T11:18:43ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/7dc634dccbcfa3428d72b03ac533a5f1ff66a566working on exceptions2015-08-10T14:16:32ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/b57333c6522d7284743bd9bb9b24aa2731cbd673top level @ SPEC card working!2015-05-28T08:40:52ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/3a06e0073bc462e350aafde45c78e1d6edb2f01eadded hello world & UART bootloader2015-05-28T08:40:16ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/8680d785b5dce7dfabaadca4655c93578b7a479bfixed WB stall2015-05-28T08:37:48ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/40e55b9a00c90a9ed88911130b61ec0802641999moved files around, added test sw2015-05-27T17:52:09ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/fa287419fb995fbbdd3c70e440e66fbe1e9902adadded barrel shifteR2015-05-27T17:49:56ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/874f587a99e11bbc6bf581069056c40ed9b3aee7wip on wishbone BIU2015-05-27T17:49:31ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/14e06a774ea72b55d998570e055cf1a54644b847fixed wait states on long reads/writes2015-05-27T17:38:59ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/b2bc141b4335dcce782eb11c9a0f6f83fedc0763shifter refactor2015-05-26T23:51:36ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/1cc11f80441b449fa09865bb494c57e4a38e2990fixed dropped jump if followed by multicycle instruction2015-05-26T18:10:13ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/a9fae1acb821e0c66346e0b1af26a7866355cd9esimplify mem address generation2015-05-26T16:30:05ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/18f2be7274db1e0c3cb88b42e911832285acb575attempt to pipeline decoding even more2015-05-26T16:12:31ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/15333cd69002cdda5212b3da58879b8c2d9ba2abremoved ugly mem2mem bypass2015-05-26T15:41:01ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/c374e8af62653a29d0ed47ff7c205bc72004682a4-stage pipeline running sorting test program2015-05-26T15:22:10ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/08a9b8d4ab382b846583377909a1dd7c49b4f9efload interlock seems to work2015-05-26T00:50:11ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/2512ebf0702a53b5b50ca1454107ddc099842033will add D stage2015-05-25T22:32:59ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/79a000cb2c59899c762fefdb1b8e5f9d226053ffadded wait states to the I/D interface. not tested yet2015-05-24T20:39:18ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/8d0fb7a5fc8a0cc7ef1e878370735815b71620e8runs sorting test, added barrel shifter and optimized a bit2015-05-24T17:37:57ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/fb33d0f11e0765f01790798a9d1db9a0edbd2ee8sorting test works2015-05-23T22:24:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/7c85788546bbf242f4d0119d4a5e869f5518076dinitial version of the core. prints 'hello world'2015-05-23T16:36:32ZTomasz Włostowskitomasz.wlostowski@cern.ch