urv-core:18f2be7274db1e0c3cb88b42e911832285acb575 commitshttps://ohwr.org/project/urv-core/commits/18f2be7274db1e0c3cb88b42e911832285acb5752015-05-26T16:12:31Zhttps://ohwr.org/project/urv-core/commit/18f2be7274db1e0c3cb88b42e911832285acb575attempt to pipeline decoding even more2015-05-26T16:12:31ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/15333cd69002cdda5212b3da58879b8c2d9ba2abremoved ugly mem2mem bypass2015-05-26T15:41:01ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/c374e8af62653a29d0ed47ff7c205bc72004682a4-stage pipeline running sorting test program2015-05-26T15:22:10ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/08a9b8d4ab382b846583377909a1dd7c49b4f9efload interlock seems to work2015-05-26T00:50:11ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/2512ebf0702a53b5b50ca1454107ddc099842033will add D stage2015-05-25T22:32:59ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/79a000cb2c59899c762fefdb1b8e5f9d226053ffadded wait states to the I/D interface. not tested yet2015-05-24T20:39:18ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/8d0fb7a5fc8a0cc7ef1e878370735815b71620e8runs sorting test, added barrel shifter and optimized a bit2015-05-24T17:37:57ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/fb33d0f11e0765f01790798a9d1db9a0edbd2ee8sorting test works2015-05-23T22:24:28ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/urv-core/commit/7c85788546bbf242f4d0119d4a5e869f5518076dinitial version of the core. prints 'hello world'2015-05-23T16:36:32ZTomasz Włostowskitomasz.wlostowski@cern.ch