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urv-core
Commits
fb33d0f1
Commit
fb33d0f1
authored
May 23, 2015
by
Tomasz Wlostowski
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sorting test works
parent
7c857885
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5 changed files
with
56 additions
and
12 deletions
+56
-12
main.sv
main.sv
+31
-4
rv_cpu.v
rv_cpu.v
+7
-1
rv_defs.v
rv_defs.v
+1
-1
rv_exec.v
rv_exec.v
+12
-5
rv_fetch.v
rv_fetch.v
+5
-1
No files found.
main.sv
View file @
fb33d0f1
...
...
@@ -102,7 +102,7 @@ module main;
initial
begin
load_ram
(
"sw/
hello
.ram"
)
;
load_ram
(
"sw/
test2/test2
.ram"
)
;
repeat
(
3
)
@
(
posedge
clk
)
;
rst
=
0
;
end
...
...
@@ -196,14 +196,41 @@ module main;
if
(
dm_write
)
$
display
(
"DM Write addr %x data %x"
,
dm_addr
,
dm_data_s
)
;
if
(
DUT
.
writeback
.
x_load_i
)
begin
if
($
isunkown
(
dm_data_l
))
begin
$
error
(
"Attempt to load uninitialized entry from memory"
)
;
$
stop
;
end
$
display
(
"DM Load addr %x data %x -> %s"
,
dm_addr_d0
,
dm_data_l
,
decode_regname
(
DUT
.
writeback
.
x_rd_i
))
;
end
end
integer
f_console
;
initial
begin
f_console
=
$
fopen
(
"console.txt"
,
"wb"
)
;
#
500u
s
;
// $fclose(f_console);
end
always
@
(
posedge
clk
)
if
(
dm_write
&&
dm_addr
==
'h100000
)
begin
$
display
(
"
\n
****** TX '%c'
\n
"
,
dm_data_s
[
7
:
0
])
;
// byte x = dm_data_s[7:0];
$
fwrite
(
f_console
,
"%c"
,
dm_data_s
[
7
:
0
])
;
$
fflush
(
f_console
)
;
end
...
...
rv_cpu.v
View file @
fb33d0f1
...
...
@@ -44,6 +44,7 @@ module rv_cpu
wire
w_stall
;
wire
x_stall
;
wire
x_kill
;
wire
f_kill
;
wire
[
31
:
0
]
f2d_pc
,
f2d_ir
;
wire
f2d_ir_valid
;
...
...
@@ -62,6 +63,8 @@ module rv_cpu
.
im_valid_i
(
im_valid_i
)
,
.
f_stall_i
(
f_stall
)
,
.
f_kill_i
(
f_kill
)
,
.
f_ir_o
(
f2d_ir
)
,
.
f_pc_o
(
f2d_pc
)
,
.
f_ir_valid_o
(
f2d_ir_valid
)
,
...
...
@@ -227,7 +230,10 @@ always@(posedge clk_i)
assign
x_stall
=
f_stall
||
(
!
f2d_ir_valid
)
;
assign
w_stall
=
x_stall
;
assign
x_kill
=
x2f_bra
&&
~
x_bra_d0
;
assign
x_kill
=
x2f_bra
;
assign
f_kill
=
x2f_bra
;
//&& ~x_bra_d0;
endmodule
// rv_cpu
...
...
rv_defs.v
View file @
fb33d0f1
...
...
@@ -31,7 +31,7 @@
`define
BRA_EQ 3
'
b000
`define
BRA_NEQ 3
'
b001
`define
BRA_LT 3
'
b100
`define
BRA_GE 3
'
b10
0
`define
BRA_GE 3
'
b10
1
`define
BRA_LTU 3
'
b110
`define
BRA_GEU 3
'
b111
...
...
rv_exec.v
View file @
fb33d0f1
...
...
@@ -92,10 +92,10 @@ module rv_exec
case
(
d_fun_i
)
`BRA_EQ
:
branch_condition_met
<=
(
rs1
==
rs2
)
;
`BRA_NEQ
:
branch_condition_met
<=
~
(
rs1
==
rs2
)
;
`BRA_GE
U
:
branch_condition_met
<=
($
signed
(
rs1
)
>=
$
signed
(
rs2
))
;
`BRA_LT
U
:
branch_condition_met
<=
($
signed
(
rs1
)
<
$
signed
(
rs2
))
;
`BRA_GE
:
branch_condition_met
<=
(
rs1
>=
rs2
)
;
`BRA_LT
:
branch_condition_met
<=
(
rs1
<
rs2
)
;
`BRA_GE
:
branch_condition_met
<=
($
signed
(
rs1
)
>=
$
signed
(
rs2
))
;
`BRA_LT
:
branch_condition_met
<=
($
signed
(
rs1
)
<
$
signed
(
rs2
))
;
`BRA_GE
U
:
branch_condition_met
<=
(
rs1
>=
rs2
)
;
`BRA_LT
U
:
branch_condition_met
<=
(
rs1
<
rs2
)
;
default:
branch_condition_met
<=
0
;
endcase
// case (d_fun_i)
...
...
@@ -115,11 +115,18 @@ module rv_exec
alu_op2
<=
(
d_opcode_i
==
`OPC_OP_IMM
)
?
d_imm_i_i
:
rs2
;
end
wire
is_subtract
=
(
d_opcode_i
==
`OPC_OP
&&
d_shifter_sign_i
)
;
// the ALU itself
always
@*
begin
case
(
d_fun_i
)
`FUNC_ADD
:
alu_result
<=
alu_op1
+
alu_op2
;
`FUNC_ADD
:
if
(
is_subtract
)
alu_result
<=
alu_op1
-
alu_op2
;
else
alu_result
<=
alu_op1
+
alu_op2
;
`FUNC_XOR
:
alu_result
<=
alu_op1
^
alu_op2
;
`FUNC_OR
:
alu_result
<=
alu_op1
|
alu_op2
;
`FUNC_AND
:
alu_result
<=
alu_op1
&
alu_op2
;
...
...
rv_fetch.v
View file @
fb33d0f1
...
...
@@ -30,6 +30,8 @@ module rv_fetch
input
im_valid_i
,
input
f_stall_i
,
input
f_kill_i
,
output
[
31
:
0
]
f_ir_o
,
output
reg
[
31
:
0
]
f_pc_o
,
...
...
@@ -61,9 +63,11 @@ module rv_fetch
rst_d
<=
1
;
if
(
!
f_stall_i
)
begin
if
(
im_valid_i
)
begin
ir
<=
im_data_i
;
f_ir_valid_o
<=
rst_d
&&
!
x_bra
_i
;
f_ir_valid_o
<=
rst_d
&&
!
f_kill
_i
;
f_pc_o
<=
pc
;
pc
<=
pc_next
;
...
...
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