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urv-core
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f54d0098
Commit
f54d0098
authored
Sep 14, 2022
by
Tristan Gingold
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urv_regfile: simplify write wire logic
parent
270c61e6
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urv_regfile.v
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rtl/urv_regfile.v
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f54d0098
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@@ -100,10 +100,7 @@ module urv_regfile
wire
[
g_width
-
1
:
0
]
rs1_regfile
;
wire
[
g_width
-
1
:
0
]
rs2_regfile
;
// By adding rst_i, register 0 is written (to 0) during reset. This is
// required on some flash FPGA (like smartfusion2 or ProASIC3) which
// doesn't support initialized RAMs.
wire
write
=
rst_i
||
(
w_rd_store_i
&&
(
w_rd_i
!=
0
))
;
wire
write
=
w_rd_store_i
;
wire
rs1_ecc_err
;
wire
rs2_ecc_err
;
...
...
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