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urv-core
Commits
d816aa08
Commit
d816aa08
authored
May 03, 2020
by
Tomasz Wlostowski
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hdl: allow to select IRAM implementation type (urv_iram/gencores)
parent
f4a94d1b
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79 additions
and
6 deletions
+79
-6
xurv_core.vhd
rtl/xurv_core.vhd
+79
-6
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rtl/xurv_core.vhd
View file @
d816aa08
...
...
@@ -29,6 +29,7 @@ entity xurv_core is
generic
(
g_internal_ram_size
:
integer
:
=
65536
;
g_internal_ram_init_file
:
string
:
=
""
;
g_internal_ram_implementation
:
string
:
=
"gencores"
;
g_simulation
:
boolean
:
=
false
;
g_address_bits
:
integer
:
=
32
);
...
...
@@ -47,6 +48,8 @@ entity xurv_core is
host_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_slave_in
;
host_slave_o
:
out
t_wishbone_slave_out
);
end
xurv_core
;
...
...
@@ -69,14 +72,46 @@ architecture wrapper of xurv_core is
dm_data_s_o
:
out
std_logic_vector
(
31
downto
0
);
dm_data_l_i
:
in
std_logic_vector
(
31
downto
0
);
dm_data_select_o
:
out
std_logic_vector
(
3
downto
0
);
dm_ready_i
:
in
std_logic
;
dm_store_o
:
out
std_logic
;
dm_load_o
:
out
std_logic
;
dm_load_done_i
:
in
std_logic
;
dm_store_done_i
:
in
std_logic
dm_store_done_i
:
in
std_logic
;
dbg_force_i
:
in
std_logic
:
=
'0'
;
dbg_enabled_o
:
out
std_logic
;
dbg_insn_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
dbg_insn_set_i
:
in
std_logic
:
=
'0'
;
dbg_insn_ready_o
:
out
std_logic
;
dbg_mbx_data_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
dbg_mbx_write_i
:
in
std_logic
:
=
'0'
;
dbg_mbx_data_o
:
out
std_logic_vector
(
31
downto
0
)
);
end
component
;
component
generic_dpram_split
is
generic
(
g_size
:
natural
;
g_addr_conflict_resolution
:
string
;
g_init_file
:
string
;
g_fail_if_file_not_found
:
boolean
);
port
(
rst_n_i
:
in
std_logic
:
=
'1'
;
clk_i
:
in
std_logic
;
bwea_i
:
in
std_logic_vector
(
3
downto
0
);
wea_i
:
in
std_logic
;
aa_i
:
in
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
);
da_i
:
in
std_logic_vector
(
31
downto
0
);
qa_o
:
out
std_logic_vector
(
31
downto
0
);
bweb_i
:
in
std_logic_vector
(
3
downto
0
);
web_i
:
in
std_logic
;
ab_i
:
in
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
);
db_i
:
in
std_logic_vector
(
31
downto
0
);
qb_o
:
out
std_logic_vector
(
31
downto
0
));
end
component
generic_dpram_split
;
component
urv_iram
generic
(
g_size
:
integer
;
...
...
@@ -114,7 +149,7 @@ architecture wrapper of xurv_core is
signal
im_addr_muxed
:
std_logic_vector
(
g_address_bits
-1
downto
0
);
signal
dm_addr
,
dm_data_s
,
dm_data_l
:
std_logic_vector
(
31
downto
0
);
signal
dm_addr
,
dm_data_s
,
dm_data_l
:
std_logic_vector
(
31
downto
0
);
signal
dm_data_select
:
std_logic_vector
(
3
downto
0
);
signal
dm_load
,
dm_store
,
dm_load_done
,
dm_store_done
,
dm_ready
:
std_logic
;
...
...
@@ -124,6 +159,8 @@ architecture wrapper of xurv_core is
signal
dm_wb_write
,
dm_select_wb
:
std_logic
;
signal
dm_data_write
:
std_logic
;
signal
s_bweb
:
std_logic_vector
(
3
downto
0
);
begin
cpu_rst
<=
(
not
rst_n_i
)
or
cpu_rst_i
;
...
...
@@ -231,7 +268,7 @@ begin
dm_data_l
<=
dm_wb_rdata
when
dm_select_wb
=
'1'
else
dm_mem_rdata
;
im_addr_muxed
<=
ha_im_addr
when
ha_im_access
=
'1'
else
im_addr
(
g_address_bits
-1
downto
0
);
dm_ready
<=
'1'
;
--
dm_ready <= '1';
cpu_core
:
urv_cpu
port
map
(
...
...
@@ -245,14 +282,18 @@ begin
dm_data_s_o
=>
dm_data_s
,
dm_data_l_i
=>
dm_data_l
,
dm_data_select_o
=>
dm_data_select
,
dm_ready_i
=>
dm_ready
,
--
dm_ready_i => dm_ready,
dm_store_o
=>
dm_store
,
dm_load_o
=>
dm_load
,
dm_load_done_i
=>
dm_load_done
,
dm_store_done_i
=>
dm_store_done
);
dm_store_done_i
=>
dm_store_done
);
dm_data_write
<=
not
dm_is_wishbone
and
dm_store
;
gen_use_urv_iram
:
if
g_internal_ram_implementation
=
"iram"
generate
U_iram
:
urv_iram
generic
map
(
g_size
=>
g_internal_ram_size
,
...
...
@@ -276,6 +317,38 @@ begin
qb_o
=>
dm_mem_rdata
);
end
generate
gen_use_urv_iram
;
gen_urv_use_genram
:
if
g_internal_ram_implementation
=
"gencores"
generate
U_IRAM
:
generic_dpram_split
generic
map
(
g_size
=>
g_internal_ram_size
/
4
,
g_init_file
=>
g_internal_ram_init_file
,
g_fail_if_file_not_found
=>
true
,
g_addr_conflict_resolution
=>
"read_first"
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_sys_i
,
bwea_i
=>
"0000"
,
wea_i
=>
'0'
,
aa_i
=>
im_addr_muxed
(
c_mem_address_bits
+
1
downto
2
),
da_i
=>
ha_im_wdata
,
qa_o
=>
im_data
,
bweb_i
=>
dm_data_select
,
web_i
=>
dm_data_write
,
ab_i
=>
dm_addr
(
c_mem_address_bits
+
1
downto
2
),
db_i
=>
dm_data_s
,
qb_o
=>
dm_mem_rdata
);
end
generate
gen_urv_use_genram
;
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
...
...
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