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urv-core
Commit d36aadc8 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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rtl: some area optimizations

parent b9db4939
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Showing with 262 additions and 208 deletions
rtl/rv_exec.v
View file @ d36aadc8
......@@ -43,6 +43,7 @@ module rv_exec
input d_valid_i,
input d_load_hazard_i,
input [4:0] d_opcode_i,
input d_shifter_sign_i,
......@@ -75,6 +76,7 @@ module rv_exec
output reg [31:0] f_branch_target_o,
output f_branch_take_o,
output w_load_hazard_o,
input irq_i,
......@@ -122,8 +124,8 @@ module rv_exec
reg [31:0] dm_addr, dm_data_s, dm_select_s;
wire [32:0] cmp_op1 = { d_is_signed_compare_i ? rs1[31] : 1'b0, rs1 };
wire [32:0] cmp_op2 = { d_is_signed_compare_i ? rs2[31] : 1'b0, rs2 };
wire [32:0] cmp_op1 = { d_is_signed_alu_op_i ? rs1[31] : 1'b0, rs1 };
wire [32:0] cmp_op2 = { d_is_signed_alu_op_i ? rs2[31] : 1'b0, rs2 };
wire [32:0] cmp_rs = cmp_op1 - cmp_op2;
......@@ -210,7 +212,7 @@ module rv_exec
// branch condition decoding
always@*
case (d_fun_i)
case (d_fun_i) // synthesis parallel_case full_case
`BRA_EQ: branch_condition_met <= cmp_equal;
`BRA_NEQ: branch_condition_met <= ~cmp_equal;
`BRA_GE: branch_condition_met <= ~cmp_lt | cmp_equal;
......@@ -219,27 +221,26 @@ module rv_exec
`BRA_LTU: branch_condition_met <= cmp_lt;
default: branch_condition_met <= 0;
endcase // case (d_fun_i)
// generate load/store address
always@*
dm_addr <= d_imm_i + ( ( d_opcode_i == `OPC_JALR || d_opcode_i == `OPC_LOAD || d_opcode_i == `OPC_STORE) ? rs1 : d_pc_i );
always@*
if(d_is_eret_i )
branch_target <= exception_address;
else if ( exception )
branch_target <= exception_vector;
else case (d_opcode_i)
`OPC_JAL: branch_target <= d_pc_i + d_imm_i;
`OPC_JALR: branch_target <= rs1 + d_imm_i;
`OPC_BRANCH: branch_target <= d_pc_i + d_imm_i;
default: branch_target<= 32'hx;
endcase // case (d_opcode_i)
// decode ALU operands
else
branch_target <= dm_addr;
// decode ALU operands
always@*
begin
alu_op1 <= d_use_op1_i ? d_alu_op1_i : rs1;
alu_op2 <= d_use_op2_i ? d_alu_op2_i : rs2;
end
wire [32:0] alu_addsub_op1 = {d_is_signed_alu_op_i ? alu_op1[31] : 1'b0, alu_op1 };
wire [32:0] alu_addsub_op2 = {d_is_signed_alu_op_i ? alu_op2[31] : 1'b0, alu_op2 };
......@@ -250,7 +251,7 @@ module rv_exec
alu_addsub_result <= alu_addsub_op1 + alu_addsub_op2;
else
alu_addsub_result <= alu_addsub_op1 - alu_addsub_op2;
// the ALU itself
always@*
......@@ -336,11 +337,6 @@ module rv_exec
default: rd_value <= 32'hx;
endcase // case (x_rd_source_i)
// generate load/store address
always@*
begin
dm_addr <= rs1 + { {20{d_imm_i[11]}}, d_imm_i[11:0] };
end
reg unaligned_addr;
......@@ -430,6 +426,7 @@ module rv_exec
w_load_o <= 0;
w_store_o <= 0;
w_valid_o <= 0;
end else if (!x_stall_i) begin
f_branch_target_o <= branch_target;
f_branch_take <= branch_take && !x_kill_i && d_valid_i;
......@@ -446,6 +443,7 @@ module rv_exec
assign f_branch_take_o = f_branch_take;
always@*
if(f_branch_take)
x_stall_req_o <= 0;
......@@ -456,6 +454,7 @@ module rv_exec
else
x_stall_req_o <= 0;
endmodule
......
rtl/rv_predecode.v
View file @ d36aadc8
......@@ -148,18 +148,13 @@ module rv_decode
end else
load_hazard <= 0;
reg inserting_nop = 0;
reg load_hazard_d;
reg inserting_nop;
always@(posedge clk_i)
if(rst_i) begin
inserting_nop <= 0;
load_hazard_d <= 0;
end else if (!d_stall_i)
begin
load_hazard_d <= load_hazard;
if (inserting_nop)
inserting_nop <= 0;
......@@ -169,7 +164,6 @@ module rv_decode
assign d_stall_req_o = load_hazard && !inserting_nop;
wire [4:0] f_rd = f_ir_i[11:7];
......@@ -213,14 +207,12 @@ module rv_decode
x_shifter_sign_o <= f_ir_i[30];
wire[31:0] d_imm_i = { {21{ f_ir_i[31] }}, f_ir_i[30:25], f_ir_i[24:21], f_ir_i[20] };
wire[31:0] d_imm_s = { {21{ f_ir_i[31] }}, f_ir_i[30:25], f_ir_i[11:8], f_ir_i[7] };
wire[31:0] d_imm_b = { {20{ f_ir_i[31] }}, f_ir_i[7], f_ir_i[30:25], f_ir_i[11:8], 1'b0 };
wire[31:0] d_imm_u = { f_ir_i[31], f_ir_i[30:20], f_ir_i[19:12], 12'h000 };
wire[31:0] d_imm_j = { {12{f_ir_i[31]}},
f_ir_i[19:12],
f_ir_i[20], f_ir_i[30:25], f_ir_i[24:21], 1'b0};
wire [31:0] d_imm_s = { {21{ f_ir_i[31] }}, f_ir_i[30:25], f_ir_i[11:8], f_ir_i[7] };
wire [31:0] d_imm_b = { {20{ f_ir_i[31] }}, f_ir_i[7], f_ir_i[30:25], f_ir_i[11:8], 1'b0 };
wire [31:0] d_imm_u = { f_ir_i[31], f_ir_i[30:20], f_ir_i[19:12], 12'h000 };
wire [31:0] d_imm_j = { {12{f_ir_i[31]}},
f_ir_i[19:12],
f_ir_i[20], f_ir_i[30:25], f_ir_i[24:21], 1'b0};
reg [31:0] d_imm;
......@@ -302,18 +294,42 @@ module rv_decode
x_is_load_o <= ( d_opcode == `OPC_LOAD && !load_hazard) ? 1'b1 : 1'b0;
x_is_store_o <= ( d_opcode == `OPC_STORE && !load_hazard) ? 1'b1 : 1'b0;
x_is_signed_compare_o <= ( ( d_opcode == `OPC_BRANCH) && ( ( d_fun == `BRA_GE )|| (d_fun == `BRA_LT ) ) )
|| ( ( (d_opcode == `OPC_OP) || (d_opcode == `OPC_OP_IMM) ) && (d_fun == `FUNC_SLT ) );
x_is_mul <= d_is_mul;
case (d_opcode)
`OPC_BRANCH:
x_is_signed_alu_op_o <= (d_fun == `BRA_GE || d_fun == `BRA_LT);
default:
x_is_signed_alu_op_o <= (d_fun == `FUNC_SLT);
endcase // case (d_opcode)
x_is_add_o <= (d_opcode == `OPC_AUIPC) || (d_opcode == `OPC_JAL) ||
case (d_opcode)
`OPC_OP:
x_is_add_o <= ~f_ir_i[30] && !(d_fun == `FUNC_SLT || d_fun == `FUNC_SLTU);
`OPC_OP_IMM:
x_is_add_o <= !(d_fun == `FUNC_SLT || d_fun == `FUNC_SLTU);
`OPC_BRANCH:
x_is_add_o <= 0;
default:
x_is_add_o <= 1;
endcase // case (d_opcode)
// x_is
// SUB instruction
// ~ ( d_opcode == OPC_OP &&
/*(d_opcode == `OPC_AUIPC) || (d_opcode == `OPC_JAL) ||
(d_opcode == `OPC_LUI) || (d_opcode == `OPC_JALR) ||
(!((d_opcode == `OPC_OP && d_fun == `FUNC_ADD && f_ir_i[30]) || (d_fun == `FUNC_SLT) || (d_fun == `FUNC_SLTU)));
(!((d_opcode == `OPC_OP && d_fun == `FUNC_ADD && f_ir_i[30]) || (d_fun == `FUNC_SLT) || (d_fun == `FUNC_SLTU)));*/
x_is_signed_alu_op_o <= (d_fun == `FUNC_SLT);
// all multiply/divide instructions except MUL
x_is_undef_o <= (d_opcode == `OPC_OP && f_ir_i[25] && d_fun != 3'b000);
......
rtl/rv_regfile.v
View file @ d36aadc8
......@@ -166,3 +166,125 @@ module rv_regfile
endmodule // rv_regfile
module rv_regmem_distram
(
input clk_i,
input [4:0] a1_i,
output [31:0] q1_o,
input [4:0] a2_i,
input [31:0] d2_i,
input we2_i
);
reg [31:0] ram [0:31];
assign q1_o = ram[a1_i];
always@(posedge clk_i)
if(we2_i)
ram[a2_i] <= d2_i;
// synthesis translate_off
initial begin : ram_init
integer i;
for(i=0;i<32; i=i+1) begin
ram[i] = 0;
end
end
// synthesis translate_on
endmodule // rv_regmem2
module rv_regfile_distram
(
input clk_i,
input rst_i,
input d_stall_i,
input [4:0] rf_rs1_i,
input [4:0] rf_rs2_i,
input [4:0] d_rs1_i,
input [4:0] d_rs2_i,
output reg [31:0] x_rs1_value_o,
output reg [31:0] x_rs2_value_o,
input [4:0] w_rd_i,
input [31:0] w_rd_value_i,
input w_rd_store_i,
input w_bypass_rd_write_i,
input [31:0] w_bypass_rd_value_i
);
wire [31:0] rs1_regfile;
wire [31:0] rs2_regfile;
wire write = (w_rd_store_i && (w_rd_i != 0));
rv_regmem_distram bank0 (
.clk_i(clk_i),
.a1_i(rf_rs1_i),
.q1_o(rs1_regfile),
.a2_i(w_rd_i),
.d2_i(w_rd_value_i),
.we2_i (write));
rv_regmem_distram bank1 (
.clk_i(clk_i),
.a1_i(rf_rs2_i),
.q1_o(rs2_regfile),
.a2_i (w_rd_i),
.d2_i (w_rd_value_i),
.we2_i (write)
);
wire rs1_bypass_x = w_bypass_rd_write_i && (w_rd_i == d_rs1_i) && (w_rd_i != 0);
wire rs2_bypass_x = w_bypass_rd_write_i && (w_rd_i == d_rs2_i) && (w_rd_i != 0);
reg rs1_bypass_w, rs2_bypass_w;
always@*
begin
rs1_bypass_w <= write && (rf_rs1_i == w_rd_i);
rs2_bypass_w <= write && (rf_rs2_i == w_rd_i);
end
always@(posedge clk_i)
if(!d_stall_i)
begin
case ( {rs1_bypass_x, rs1_bypass_w } ) // synthesis parallel_case full_case
2'b10, 2'b11:
x_rs1_value_o <= w_bypass_rd_value_i;
2'b01:
x_rs1_value_o <= w_rd_value_i;
default:
x_rs1_value_o <= rs1_regfile;
endcase // case ( {rs1_bypass_x, rs1_bypass_w } )
case ( {rs2_bypass_x, rs2_bypass_w } ) // synthesis parallel_case full_case
2'b10, 2'b11:
x_rs2_value_o <= w_bypass_rd_value_i;
2'b01:
x_rs2_value_o <= w_rd_value_i;
default:
x_rs2_value_o <= rs2_regfile;
endcase // case ( {rs2_bypass_x, rs2_bypass_w } )
end // always@ *
endmodule // rv_regfile
tb/cpu/run.do
View file @ d36aadc8
#vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include +incdir+../include +incdir+../../sim
vsim -t 1ps work.main -novopt
vsim -L unisim -t 1ps work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
tb/cpu/wave.do
View file @ d36aadc8
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group F /main/DUT/fetch/clk_i
add wave -noupdate -expand -group F /main/DUT/fetch/rst_i
add wave -noupdate -expand -group F /main/DUT/fetch/im_addr_o
add wave -noupdate -expand -group F /main/DUT/fetch/im_data_i
add wave -noupdate -expand -group F /main/DUT/fetch/im_valid_i
add wave -noupdate -expand -group F /main/DUT/fetch/f_stall_i
add wave -noupdate -expand -group F /main/DUT/fetch/f_kill_i
add wave -noupdate -expand -group F /main/DUT/fetch/f_ir_o
add wave -noupdate -expand -group F /main/DUT/fetch/f_pc_o
add wave -noupdate -expand -group F /main/DUT/fetch/f_pc_plus_4_o
add wave -noupdate -expand -group F /main/DUT/fetch/f_valid_o
add wave -noupdate -expand -group F /main/DUT/fetch/x_pc_bra_i
add wave -noupdate -expand -group F /main/DUT/fetch/x_bra_i
add wave -noupdate -expand -group F /main/DUT/fetch/pc
add wave -noupdate -expand -group F /main/DUT/fetch/pc_plus_4
add wave -noupdate -expand -group F /main/DUT/fetch/ir
add wave -noupdate -expand -group F /main/DUT/fetch/rst_d
add wave -noupdate -expand -group F /main/DUT/fetch/pc_next
add wave -noupdate -expand -group D /main/DUT/decode/clk_i
add wave -noupdate -expand -group D /main/DUT/decode/rst_i
add wave -noupdate -expand -group D /main/DUT/decode/d_stall_i
add wave -noupdate -expand -group D /main/DUT/decode/d_kill_i
add wave -noupdate -expand -group D /main/DUT/decode/d_stall_req_o
add wave -noupdate -expand -group D /main/DUT/decode/x_load_hazard_o
add wave -noupdate -expand -group D /main/DUT/decode/f_ir_i
add wave -noupdate -expand -group D /main/DUT/decode/f_pc_i
add wave -noupdate -expand -group D /main/DUT/decode/f_valid_i
add wave -noupdate -expand -group D /main/DUT/decode/x_valid_o
add wave -noupdate -expand -group D /main/DUT/decode/x_pc_o
add wave -noupdate -expand -group D /main/DUT/decode/rf_rs1_o
add wave -noupdate -expand -group D /main/DUT/decode/rf_rs2_o
add wave -noupdate -expand -group D /main/DUT/decode/x_rs1_o
add wave -noupdate -expand -group D /main/DUT/decode/x_rs2_o
add wave -noupdate -expand -group D /main/DUT/decode/x_rd_o
add wave -noupdate -expand -group D /main/DUT/decode/x_shamt_o
add wave -noupdate -expand -group D /main/DUT/decode/x_fun_o
add wave -noupdate -expand -group D /main/DUT/decode/x_opcode_o
add wave -noupdate -expand -group D /main/DUT/decode/x_shifter_sign_o
add wave -noupdate -expand -group D /main/DUT/decode/x_imm_o
add wave -noupdate -expand -group D /main/DUT/decode/x_is_signed_compare_o
add wave -noupdate -expand -group D /main/DUT/decode/x_is_signed_alu_op_o
add wave -noupdate -expand -group D /main/DUT/decode/x_is_add_o
add wave -noupdate -expand -group D /main/DUT/decode/x_is_shift_o
add wave -noupdate -expand -group D /main/DUT/decode/x_rd_source_o
add wave -noupdate -expand -group D /main/DUT/decode/x_rd_write_o
add wave -noupdate -expand -group D /main/DUT/decode/x_is_undef_o
add wave -noupdate -expand -group D /main/DUT/decode/x_csr_sel_o
add wave -noupdate -expand -group D /main/DUT/decode/x_csr_imm_o
add wave -noupdate -expand -group D /main/DUT/decode/x_is_csr_o
add wave -noupdate -expand -group D /main/DUT/decode/x_is_eret_o
add wave -noupdate -expand -group D /main/DUT/decode/f_rs1
add wave -noupdate -expand -group D /main/DUT/decode/f_rs2
add wave -noupdate -expand -group D /main/DUT/decode/x_rs1
add wave -noupdate -expand -group D /main/DUT/decode/x_rs2
add wave -noupdate -expand -group D /main/DUT/decode/x_rd
add wave -noupdate -expand -group D /main/DUT/decode/x_opcode
add wave -noupdate -expand -group D /main/DUT/decode/x_ir
add wave -noupdate -expand -group D /main/DUT/decode/d_opcode
add wave -noupdate -expand -group D /main/DUT/decode/load_hazard
add wave -noupdate -expand -group D /main/DUT/decode/inserting_nop
add wave -noupdate -expand -group D /main/DUT/decode/d_fun
add wave -noupdate -expand -group D /main/DUT/decode/d_imm_i
add wave -noupdate -expand -group D /main/DUT/decode/d_imm_s
add wave -noupdate -expand -group D /main/DUT/decode/d_imm_b
add wave -noupdate -expand -group D /main/DUT/decode/d_imm_u
add wave -noupdate -expand -group D /main/DUT/decode/d_imm_j
add wave -noupdate -expand -group D /main/DUT/decode/d_is_shift
add wave -noupdate -group RF /main/DUT/regfile/clk_i
add wave -noupdate -group RF /main/DUT/regfile/rst_i
add wave -noupdate -group RF /main/DUT/regfile/x_stall_i
add wave -noupdate -group RF /main/DUT/regfile/w_stall_i
add wave -noupdate -group RF /main/DUT/regfile/rf_rs1_i
add wave -noupdate -group RF /main/DUT/regfile/rf_rs2_i
add wave -noupdate -group RF /main/DUT/regfile/d_rs1_i
add wave -noupdate -group RF /main/DUT/regfile/d_rs2_i
add wave -noupdate -group RF /main/DUT/regfile/x_rs1_value_o
add wave -noupdate -group RF /main/DUT/regfile/x_rs2_value_o
add wave -noupdate -group RF /main/DUT/regfile/w_rd_i
add wave -noupdate -group RF /main/DUT/regfile/w_rd_value_i
add wave -noupdate -group RF /main/DUT/regfile/w_rd_store_i
add wave -noupdate -group RF /main/DUT/regfile/w_bypass_rd_write_i
add wave -noupdate -group RF /main/DUT/regfile/w_bypass_rd_value_i
add wave -noupdate -group RF /main/DUT/regfile/rs1_regfile
add wave -noupdate -group RF /main/DUT/regfile/rs2_regfile
add wave -noupdate -group RF /main/DUT/regfile/write
add wave -noupdate -group RF /main/DUT/regfile/rs1_bypass
add wave -noupdate -group RF /main/DUT/regfile/rs2_bypass
add wave -noupdate -group RF -expand /main/DUT/regfile/bank0/ram
add wave -noupdate -group RF /main/cycles
add wave -noupdate -group D /main/DUT/decode/clk_i
add wave -noupdate -group D /main/DUT/decode/rst_i
add wave -noupdate -group D /main/DUT/decode/d_stall_i
add wave -noupdate -group D /main/DUT/decode/d_kill_i
add wave -noupdate -group D /main/DUT/decode/d_stall_req_o
add wave -noupdate -group D /main/DUT/decode/x_load_hazard_o
add wave -noupdate -group D /main/DUT/decode/f_ir_i
add wave -noupdate -group D /main/DUT/decode/f_pc_i
add wave -noupdate -group D /main/DUT/decode/f_valid_i
add wave -noupdate -group D /main/DUT/decode/x_valid_o
add wave -noupdate -group D /main/DUT/decode/x_pc_o
add wave -noupdate -group D /main/DUT/decode/rf_rs1_o
add wave -noupdate -group D /main/DUT/decode/rf_rs2_o
add wave -noupdate -group D /main/DUT/decode/x_rs1_o
add wave -noupdate -group D /main/DUT/decode/x_rs2_o
add wave -noupdate -group D /main/DUT/decode/x_rd_o
add wave -noupdate -group D /main/DUT/decode/x_shamt_o
add wave -noupdate -group D /main/DUT/decode/x_fun_o
add wave -noupdate -group D /main/DUT/decode/x_opcode_o
add wave -noupdate -group D /main/DUT/decode/x_shifter_sign_o
add wave -noupdate -group D /main/DUT/decode/x_is_signed_compare_o
add wave -noupdate -group D /main/DUT/decode/x_is_signed_alu_op_o
add wave -noupdate -group D /main/DUT/decode/x_is_add_o
add wave -noupdate -group D /main/DUT/decode/x_is_shift_o
add wave -noupdate -group D /main/DUT/decode/x_is_load_o
add wave -noupdate -group D /main/DUT/decode/x_is_store_o
add wave -noupdate -group D /main/DUT/decode/x_is_undef_o
add wave -noupdate -group D /main/DUT/decode/x_rd_source_o
add wave -noupdate -group D /main/DUT/decode/x_rd_write_o
add wave -noupdate -group D /main/DUT/decode/x_csr_sel_o
add wave -noupdate -group D /main/DUT/decode/x_csr_imm_o
add wave -noupdate -group D /main/DUT/decode/x_is_csr_o
add wave -noupdate -group D /main/DUT/decode/x_is_eret_o
add wave -noupdate -group D /main/DUT/decode/x_alu_op1_o
add wave -noupdate -group D /main/DUT/decode/x_alu_op2_o
add wave -noupdate -group D /main/DUT/decode/x_use_op1_o
add wave -noupdate -group D /main/DUT/decode/x_use_op2_o
add wave -noupdate -group D /main/DUT/decode/f_rs1
add wave -noupdate -group D /main/DUT/decode/f_rs2
add wave -noupdate -group D /main/DUT/decode/x_rs1
add wave -noupdate -group D /main/DUT/decode/x_rs2
add wave -noupdate -group D /main/DUT/decode/x_rd
add wave -noupdate -group D /main/DUT/decode/x_opcode
add wave -noupdate -group D /main/DUT/decode/x_valid
add wave -noupdate -group D /main/DUT/decode/x_is_shift
add wave -noupdate -group D /main/DUT/decode/x_rd_write
add wave -noupdate -group D /main/DUT/decode/x_ir
add wave -noupdate -group D /main/DUT/decode/d_opcode
add wave -noupdate -group D /main/DUT/decode/load_hazard
add wave -noupdate -group D /main/DUT/decode/d_fun
add wave -noupdate -group D /main/DUT/decode/d_is_shift
add wave -noupdate -group D /main/DUT/decode/x_is_mul
add wave -noupdate -group D /main/DUT/decode/d_is_mul
add wave -noupdate -group D /main/DUT/decode/inserting_nop
add wave -noupdate -group D /main/DUT/decode/load_hazard_d
add wave -noupdate -group D /main/DUT/decode/d_imm_i
add wave -noupdate -group D /main/DUT/decode/d_imm_s
add wave -noupdate -group D /main/DUT/decode/d_imm_b
add wave -noupdate -group D /main/DUT/decode/d_imm_u
add wave -noupdate -group D /main/DUT/decode/d_imm_j
add wave -noupdate -group D /main/DUT/decode/x_imm
add wave -noupdate -expand -group X /main/DUT/execute/clk_i
add wave -noupdate -expand -group X /main/DUT/execute/rst_i
add wave -noupdate -expand -group X -radix decimal /main/cycles
add wave -noupdate -expand -group X /main/DUT/execute/x_stall_i
add wave -noupdate -expand -group X /main/DUT/execute/x_kill_i
add wave -noupdate -expand -group X /main/DUT/execute/x_stall_req_o
......@@ -117,6 +88,10 @@ add wave -noupdate -expand -group X /main/DUT/execute/d_is_load_i
add wave -noupdate -expand -group X /main/DUT/execute/d_is_store_i
add wave -noupdate -expand -group X /main/DUT/execute/d_is_divide_i
add wave -noupdate -expand -group X /main/DUT/execute/d_is_undef_i
add wave -noupdate -expand -group X /main/DUT/execute/d_alu_op1_i
add wave -noupdate -expand -group X /main/DUT/execute/d_alu_op2_i
add wave -noupdate -expand -group X /main/DUT/execute/d_use_op1_i
add wave -noupdate -expand -group X /main/DUT/execute/d_use_op2_i
add wave -noupdate -expand -group X /main/DUT/execute/d_rd_source_i
add wave -noupdate -expand -group X /main/DUT/execute/d_rd_write_i
add wave -noupdate -expand -group X /main/DUT/execute/f_branch_target_o
......@@ -126,10 +101,14 @@ add wave -noupdate -expand -group X /main/DUT/execute/irq_i
add wave -noupdate -expand -group X /main/DUT/execute/w_fun_o
add wave -noupdate -expand -group X /main/DUT/execute/w_load_o
add wave -noupdate -expand -group X /main/DUT/execute/w_store_o
add wave -noupdate -expand -group X /main/DUT/execute/w_valid_o
add wave -noupdate -expand -group X /main/DUT/execute/w_rd_o
add wave -noupdate -expand -group X /main/DUT/execute/w_rd_value_o
add wave -noupdate -expand -group X /main/DUT/execute/w_rd_write_o
add wave -noupdate -expand -group X /main/DUT/execute/w_dm_addr_o
add wave -noupdate -expand -group X /main/DUT/execute/w_rd_source_o
add wave -noupdate -expand -group X /main/DUT/execute/w_rd_shifter_o
add wave -noupdate -expand -group X /main/DUT/execute/w_rd_multiply_o
add wave -noupdate -expand -group X /main/DUT/execute/dm_addr_o
add wave -noupdate -expand -group X /main/DUT/execute/dm_data_s_o
add wave -noupdate -expand -group X /main/DUT/execute/dm_data_select_o
......@@ -162,92 +141,22 @@ add wave -noupdate -expand -group X /main/DUT/execute/rd_csr
add wave -noupdate -expand -group X /main/DUT/execute/rd_mul
add wave -noupdate -expand -group X /main/DUT/execute/rd_div
add wave -noupdate -expand -group X /main/DUT/execute/exception
add wave -noupdate -expand -group X /main/DUT/execute/exception_vector
add wave -noupdate -expand -group X /main/DUT/execute/csr_mie
add wave -noupdate -expand -group X /main/DUT/execute/csr_mip
add wave -noupdate -expand -group X /main/DUT/execute/csr_mepc
add wave -noupdate -expand -group X /main/DUT/execute/csr_mstatus
add wave -noupdate -expand -group X /main/DUT/execute/csr_mcause
add wave -noupdate -expand -group X /main/DUT/execute/csr_write_value
add wave -noupdate -expand -group X /main/DUT/execute/exception_address
add wave -noupdate -expand -group X /main/DUT/execute/exception_vector
add wave -noupdate -expand -group X /main/DUT/execute/alu_addsub_op1
add wave -noupdate -expand -group X /main/DUT/execute/alu_addsub_op2
add wave -noupdate -expand -group X /main/DUT/execute/alu_addsub_result
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/clk_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/rst_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/x_stall_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/x_kill_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/d_is_csr_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/d_fun_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/d_csr_imm_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/d_csr_sel_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/exp_irq_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/exp_tick_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/exp_breakpoint_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/exp_unaligned_load_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/exp_unaligned_store_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/exp_invalid_insn_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/x_csr_write_value_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/x_exception_o
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/x_exception_pc_i
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/x_exception_pc_o
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_mstatus_o
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_mip_o
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_mie_o
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_mepc_o
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_mcause_o
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_mepc
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_mie
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_ie
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/exception
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/cause
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/except_vec_masked
add wave -noupdate -group ExceptionUnit /main/DUT/execute/exception_unit/csr_mip
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/clk_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/rst_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/x_stall_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/x_kill_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/d_is_csr_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/d_fun_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/d_csr_imm_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/d_csr_sel_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/d_rs1_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/x_rd_o
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_time_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_cycles_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/x_csr_write_value_o
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_mstatus_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_mip_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_mie_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_mepc_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_mcause_i
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_mscratch
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_in1
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_in2
add wave -noupdate -group CSR /main/DUT/execute/csr_regs/csr_out
add wave -noupdate -expand -group WB /main/DUT/writeback/clk_i
add wave -noupdate -expand -group WB /main/DUT/writeback/rst_i
add wave -noupdate -expand -group WB /main/DUT/writeback/w_stall_i
add wave -noupdate -expand -group WB /main/DUT/writeback/w_stall_req_o
add wave -noupdate -expand -group WB /main/DUT/writeback/x_fun_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_load_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_store_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_load_hazard_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_dm_addr_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_rd_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_rd_value_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_rd_write_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_shifter_rd_value_i
add wave -noupdate -expand -group WB /main/DUT/writeback/x_rd_source_i
add wave -noupdate -expand -group WB /main/DUT/writeback/dm_data_l_i
add wave -noupdate -expand -group WB /main/DUT/writeback/dm_load_done_i
add wave -noupdate -expand -group WB /main/DUT/writeback/dm_store_done_i
add wave -noupdate -expand -group WB /main/DUT/writeback/rf_rd_value_o
add wave -noupdate -expand -group WB /main/DUT/writeback/rf_rd_o
add wave -noupdate -expand -group WB /main/DUT/writeback/rf_rd_write_o
add wave -noupdate -expand -group WB /main/DUT/writeback/TRIG2
add wave -noupdate -expand -group WB /main/DUT/writeback/load_value
add wave -noupdate -expand -group X /main/DUT/execute/divider_stall_req
add wave -noupdate -expand -group X /main/DUT/execute/d_fun
add wave -noupdate -expand -group X /main/DUT/execute/unaligned_addr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2279679 ps} 0}
WaveRestoreCursors {{Cursor 1} {58892 ps} 0}
configure wave -namecolwidth 250
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -262,4 +171,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {2205824 ps} {2350464 ps}
WaveRestoreZoom {0 ps} {144640 ps}
tb/isa-testsuite/main.sv
View file @ d36aadc8
......@@ -49,6 +49,14 @@ module main;
int f = $fopen(filename,"r");
int n, i;
if( f == 0)
begin
$error("can't open: %s", filename);
$stop;
end
while(!$feof(f))
begin
int addr, data;
......
tb/isa-testsuite/run.do
View file @ d36aadc8
#vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include +incdir+../include +incdir+../../sim
vsim -t 1ps work.main -novopt
vsim -L unisim -t 1ps work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
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