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urv-core
Commit d005da1f authored by Tristan Gingold's avatar Tristan Gingold
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rtl: add x_use_rs1/rs2, reformatting

parent f6f20976
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Showing with 83 additions and 58 deletions
rtl/urv_cpu.v
View file @ d005da1f
......@@ -131,6 +131,7 @@ module urv_cpu
wire d2x_is_csr, d2x_is_mret, d2x_is_ebreak, d2x_csr_load_en;
wire [31:0] d2x_alu_op1, d2x_alu_op2;
wire d2x_use_op1, d2x_use_op2;
wire d2x_use_rs1, d2x_use_rs2;
wire d2x_is_multiply, d2x_is_divide;
// X1/M->X2/W interface
......@@ -223,6 +224,8 @@ module urv_cpu
.x_pc_o(d2x_pc),
.x_rs1_o(d2x_rs1),
.x_rs2_o(d2x_rs2),
.x_use_rs1_o(d2x_use_rs1),
.x_use_rs2_o(d2x_use_rs2),
.x_imm_o(d2x_imm),
.x_rd_o(d2x_rd),
.x_fun_o(d2x_fun),
......@@ -319,6 +322,8 @@ module urv_cpu
.d_alu_op2_i(d2x_alu_op2),
.d_use_op1_i(d2x_use_op1),
.d_use_op2_i(d2x_use_op2),
.d_use_rs1_i(d2x_use_rs1),
.d_use_rs2_i(d2x_use_rs2),
.d_rd_source_i(d2x_rd_source),
.d_rd_write_i(d2x_rd_write),
.d_opcode_i(d2x_opcode),
......
rtl/urv_csr.v
View file @ d005da1f
......@@ -108,8 +108,6 @@ module urv_csr
endcase // case (d_fun_i)
generate
for (i=0;i<32;i=i+1)
begin : gen_csr_bits
......@@ -128,8 +126,7 @@ module urv_csr
csr_out[i] <= 32'hx;
endcase // case (d_csr_op_i)
end // for (i=0;i<32;i=i+1)
endgenerate
endgenerate
always@(posedge clk_i)
......
rtl/urv_decode.v
View file @ d005da1f
......@@ -67,13 +67,15 @@ module urv_decode
output reg [11:0] x_csr_sel_o,
output reg [4:0] x_csr_imm_o,
output reg x_is_csr_o,
output reg x_is_mret_o,
output reg x_is_ebreak_o,
output reg x_is_mret_o,
output reg x_is_ebreak_o,
output reg [31:0] x_imm_o,
output reg [31:0] x_alu_op1_o,
output reg [31:0] x_alu_op2_o,
output reg x_use_op1_o,
output reg x_use_op2_o,
output reg x_use_rs1_o,
output reg x_use_rs2_o,
output reg x_is_divide_o,
output reg x_is_multiply_o
);
......@@ -264,6 +266,31 @@ module urv_decode
endcase // case (d_opcode_i)
end // if (!d_stall_i)
always@(posedge clk_i)
if(!d_stall_i)
case (d_opcode)
`OPC_JALR, `OPC_LOAD, `OPC_OP_IMM:
begin
x_use_rs1_o <= 1'b1;
x_use_rs2_o <= 1'b0;
end
`OPC_STORE, `OPC_BRANCH, `OPC_OP, `OPC_CUST2:
begin
x_use_rs1_o <= 1'b1;
x_use_rs2_o <= 1'b1;
end
`OPC_SYSTEM:
begin
x_use_rs1_o <= d_fun[2] == 1'b0 && d_fun[1:0] != 2'b0;
x_use_rs2_o <= 1'b0;
end
default:
begin
x_use_rs1_o <= 1'b0;
x_use_rs2_o <= 1'b0;
end
endcase
wire d_rd_nonzero = (f_rd != 0);
......
rtl/urv_defs.v
View file @ d005da1f
......@@ -39,6 +39,7 @@
`define OPC_JAL 5'b11011
`define OPC_SYSTEM 5'b11100
// funct3 for OPC_BRANCH
`define BRA_EQ 3'b000
`define BRA_NEQ 3'b001
`define BRA_LT 3'b100
......@@ -46,12 +47,14 @@
`define BRA_LTU 3'b110
`define BRA_GEU 3'b111
// funct3 for OPC_LOAD and OPC_STORE
`define LDST_B 3'b000
`define LDST_H 3'b001
`define LDST_L 3'b010
`define LDST_BU 3'b100
`define LDST_HU 3'b101
// funct3 for OPC_OP and OPC_OP_IMM
`define FUNC_ADD 3'b000
`define FUNC_SLT 3'b010
`define FUNC_SLTU 3'b011
......@@ -61,16 +64,25 @@
`define FUNC_SL 3'b001
`define FUNC_SR 3'b101
// funct3 for OPC_OP, funct7=1
`define FUNC_MUL 3'b000
`define FUNC_MULH 3'b001
`define FUNC_MULHSU 3'b010
`define FUNC_MULHU 3'b011
`define FUNC_DIV 3'b100
`define FUNC_DIVU 3'b101
`define FUNC_REM 3'b110
`define FUNC_REMU 3'b111
// funct3 for OPC_SYSTEM
`define CSR_OP_CSRRW 3'b001
`define CSR_OP_CSRRS 3'b010
`define CSR_OP_CSRRC 3'b011
`define CSR_OP_CSRRWI 3'b101
`define CSR_OP_CSRRSI 3'b110
`define CSR_OP_CSRRCI 3'b111
`define RD_SOURCE_ALU 3'b000
`define RD_SOURCE_SHIFTER 3'b010
`define RD_SOURCE_MULTIPLY 3'b001
......@@ -97,13 +109,6 @@
2019_0131: data memory wait state.
*/
`define CSR_OP_CSRRW 3'b001
`define CSR_OP_CSRRS 3'b010
`define CSR_OP_CSRRC 3'b011
`define CSR_OP_CSRRWI 3'b101
`define CSR_OP_CSRRSI 3'b110
`define CSR_OP_CSRRCI 3'b111
`define URV_RESET_VECTOR 32'h00000000
`define URV_TRAP_VECTOR 32'h00000008
......@@ -116,9 +121,9 @@
`define CAUSE_BREAKPOINT 3
`define CAUSE_UNALIGNED_LOAD 4
`define CAUSE_UNALIGNED_STORE 6
`define CAUSE_MACHINE_IRQ 11
`define CAUSE_MACHINE_TIMER 7
`define CAUSE_MACHINE_IRQ 11
`define CAUSE_ECC_ERROR 15
`define OP_SEL_BYPASS_X 0
`define OP_SEL_BYPASS_W 1
......
rtl/urv_exec.v
View file @ d005da1f
......@@ -53,9 +53,9 @@ module urv_exec
input d_shifter_sign_i,
input d_is_csr_i,
input d_is_mret_i,
input d_is_ebreak_i,
input d_dbg_mode_i,
input d_is_mret_i,
input d_is_ebreak_i,
input d_dbg_mode_i,
input [4:0] d_csr_imm_i,
input [11:0] d_csr_sel_i,
......@@ -74,13 +74,15 @@ module urv_exec
input d_use_op1_i,
input d_use_op2_i,
input d_use_rs1_i,
input d_use_rs2_i,
input [2:0] d_rd_source_i,
input d_rd_write_i,
output reg [31:0] f_branch_target_o,
output f_branch_take_o,
output reg f_dbg_toggle_o,
output reg f_dbg_toggle_o,
input irq_i,
......@@ -112,7 +114,7 @@ module urv_exec
// Debug mailboxes.
input [31:0] dbg_mbx_data_i,
input dbg_mbx_write_i,
input dbg_mbx_write_i,
output [31:0] dbg_mbx_data_o
);
......@@ -120,6 +122,7 @@ module urv_exec
parameter g_with_hw_div = 0;
parameter g_with_hw_debug = 0;
// Use rs1 and rs2, it's shorter; but keep long name for the ports.
wire [31:0] rs1, rs2;
assign rs1 = rf_rs1_value_i;
......@@ -232,13 +235,13 @@ module urv_exec
// branch condition decoding
always@*
case (d_fun_i) // synthesis parallel_case full_case
`BRA_EQ: branch_condition_met <= cmp_equal;
`BRA_EQ: branch_condition_met <= cmp_equal;
`BRA_NEQ: branch_condition_met <= ~cmp_equal;
`BRA_GE: branch_condition_met <= ~cmp_lt | cmp_equal;
`BRA_LT: branch_condition_met <= cmp_lt;
`BRA_GE: branch_condition_met <= ~cmp_lt | cmp_equal;
`BRA_LT: branch_condition_met <= cmp_lt;
`BRA_GEU: branch_condition_met <= ~cmp_lt | cmp_equal;
`BRA_LTU: branch_condition_met <= cmp_lt;
default: branch_condition_met <= 0;
default: branch_condition_met <= 0;
endcase // case (d_fun_i)
// calculate branch target address
......@@ -272,23 +275,15 @@ module urv_exec
// the rest of the ALU
always@*
begin
case (d_fun_i)
`FUNC_ADD:
alu_result <= alu_addsub_result[31:0];
`FUNC_XOR:
alu_result <= alu_op1 ^ alu_op2;
`FUNC_OR:
alu_result <= alu_op1 | alu_op2;
`FUNC_AND:
alu_result <= alu_op1 & alu_op2;
`FUNC_SLT:
alu_result <= alu_addsub_result[32]?1:0;
`FUNC_SLTU:
alu_result <= alu_addsub_result[32]?1:0;
default: alu_result <= 32'hx;
endcase // case (d_fun_i)
end // always@ *
case (d_fun_i)
`FUNC_ADD: alu_result <= alu_addsub_result[31:0];
`FUNC_XOR: alu_result <= alu_op1 ^ alu_op2;
`FUNC_OR: alu_result <= alu_op1 | alu_op2;
`FUNC_AND: alu_result <= alu_op1 & alu_op2;
`FUNC_SLT: alu_result <= alu_addsub_result[32]?1:0;
`FUNC_SLTU: alu_result <= alu_addsub_result[32]?1:0;
default: alu_result <= 32'hx;
endcase // case (d_fun_i)
// barel shifter
urv_shifter shifter
......@@ -368,8 +363,8 @@ module urv_exec
`RD_SOURCE_CSR: rd_value <= rd_csr;
`RD_SOURCE_DIVIDE: rd_value <= g_with_hw_div ? rd_divide : 32'hx;
`RD_SOURCE_MULH: rd_value <= g_with_hw_mul > 1 ? rd_mulh : 32'hx;
default: rd_value <= 32'hx;
endcase // case (x_rd_source_i)
default: rd_value <= 32'hx;
endcase
// generate load/store address
assign dm_addr = d_imm_i + rs1;
......@@ -392,7 +387,6 @@ module urv_exec
unaligned_addr <= 0;
endcase // case (d_fun_i)
// x_exception: exception due to execution
always@*
begin
......
rtl/urv_multiply.v
View file @ d005da1f
......@@ -173,10 +173,10 @@ module urv_multiply
input [31:0] d_rs2_i,
input [2:0] d_fun_i,
input d_is_multiply_i,
// multiply result for MUL instructions, bypassed to W-stage to achieve 1-cycle performance
// without much penalty on clock speed
output reg [31:0] w_rd_o,
output [31:0] w_rd_o,
// multiply result for MULH(S)(U) instructions. Goes to the X stage
// destination value mux.
......@@ -198,7 +198,7 @@ module urv_multiply
wire signed [35:0] xh_yh;
wire signed [35:0] yl_xl, yl_xh, yh_xl;
reg mul_stall_req;
wire mul_stall_req;
reg mul_stall_req_d0;
reg mul_stall_req_d1;
......@@ -265,8 +265,7 @@ module urv_multiply
begin
assign mul_result = yl_xl_ext + yh_xl_ext + yl_xh_ext + yh_xh_ext;
always@(*)
mul_stall_req <= !x_kill_i && !mul_stall_req_d1 && d_is_multiply_i && d_fun_i != `FUNC_MUL;
assign mul_stall_req = !x_kill_i && !mul_stall_req_d1 && d_is_multiply_i && d_fun_i != `FUNC_MUL;
always@(posedge clk_i)
x_rd_o <= mul_result[63:32];
......@@ -286,15 +285,13 @@ module urv_multiply
begin
assign mul_result = yl_xl + {yl_xh[14:0], 17'h0} + {yh_xl[14:0], 17'h0};
always@*
mul_stall_req <= 1'b0;
assign mul_stall_req = 1'b0;
end // else: !if(g_with_hw_mulh)
endgenerate
assign x_stall_req_o = mul_stall_req;
always@*
w_rd_o <= mul_result[31:0];
assign w_rd_o = mul_result[31:0];
endmodule // urv_multiply
rtl/urv_writeback.v
View file @ d005da1f
......@@ -73,7 +73,7 @@ module urv_writeback
2'b11: load_value <= {{24{dm_data_l_i[31]}}, dm_data_l_i[31:24] };
default: load_value <= 32'hx;
endcase // case ( x_dm_addr_i [1:0] )
`LDST_BU:
case ( x_dm_addr_i [1:0] )
2'b00: load_value <= {24'h0, dm_data_l_i[7:0] };
......@@ -82,7 +82,7 @@ module urv_writeback
2'b11: load_value <= {24'h0, dm_data_l_i[31:24] };
default: load_value <= 32'hx;
endcase // case ( x_dm_addr_i [1:0] )
`LDST_H:
case ( x_dm_addr_i [1:0] )
2'b00, 2'b01: load_value <= {{16{dm_data_l_i[15]}}, dm_data_l_i[15:0] };
......@@ -96,7 +96,7 @@ module urv_writeback
2'b10, 2'b11: load_value <= {16'h0, dm_data_l_i[31:16] };
default: load_value <= 32'hx;
endcase // case ( x_dm_addr_i [1:0] )
`LDST_L: load_value <= dm_data_l_i;
default: load_value <= 32'hx;
......@@ -105,7 +105,7 @@ module urv_writeback
reg rf_rd_write;
reg [31:0] rf_rd_value;
always@*
if( x_load_i )
rf_rd_value <= load_value;
......
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