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urv-core
Commits
9016844b
Commit
9016844b
authored
Mar 11, 2018
by
Tomasz Wlostowski
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core: fixed incorrect exception handling (exception address delayed by 1 instruction)
parent
f1fcd338
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5 changed files
with
157 additions
and
84 deletions
+157
-84
urv_exceptions.v
rtl/urv_exceptions.v
+7
-1
urv_exec.v
rtl/urv_exec.v
+3
-7
Manifest.py
tb/isa-testsuite/Manifest.py
+1
-1
main.sv
tb/isa-testsuite/main.sv
+18
-29
wave.do
tb/isa-testsuite/wave.do
+128
-46
No files found.
rtl/urv_exceptions.v
View file @
9016844b
...
...
@@ -74,6 +74,9 @@ module urv_exceptions
reg
[
5
:
0
]
except_vec_masked
;
reg
exception_pending
;
reg
[
31
:
0
]
x_exception_pc_d
;
assign
csr_mcause_o
=
{
28'h0
,
csr_mcause
};
assign
csr_mepc_o
=
csr_mepc
;
assign
csr_mie_o
=
csr_mie
;
...
...
@@ -157,11 +160,14 @@ module urv_exceptions
exception_pending
<=
0
;
end
else
if
(
!
x_stall_i
&&
!
x_kill_i
)
begin
x_exception_pc_d
<=
x_exception_pc_i
;
if
(
d_is_eret_i
)
exception_pending
<=
0
;
else
if
(
x_exception_taken_i
)
begin
csr_mepc
<=
x_exception_pc_
i
;
csr_mepc
<=
x_exception_pc_
d
;
csr_mcause
<=
cause
;
exception_pending
<=
1
;
end
...
...
rtl/urv_exec.v
View file @
9016844b
...
...
@@ -44,8 +44,6 @@ module urv_exec
input
d_valid_i
,
input
d_load_hazard_i
,
input
[
4
:
0
]
d_opcode_i
,
input
d_shifter_sign_i
,
...
...
@@ -77,8 +75,6 @@ module urv_exec
output
reg
[
31
:
0
]
f_branch_target_o
,
output
f_branch_take_o
,
output
w_load_hazard_o
,
input
irq_i
,
// Writeback stage I/F
...
...
@@ -436,9 +432,9 @@ module urv_exec
w_rd_o
<=
d_rd_i
;
w_rd_value_o
<=
rd_value
;
w_rd_write_o
<=
d_rd_write_i
&&
!
x_kill_i
&&
d_valid_i
&&
!
exception
;
w_load_o
<=
d_is_load_i
&&
!
x_kill_i
&&
d_valid_i
&&
!
exception
;
w_store_o
<=
d_is_store_i
&&
!
x_kill_i
&&
d_valid_i
&&
!
exception
;
w_rd_write_o
<=
d_rd_write_i
&&
!
x_kill_i
&&
d_valid_i
&&
!
exception
&&
!
d_is_undef_i
;
w_load_o
<=
d_is_load_i
&&
!
x_kill_i
&&
d_valid_i
&&
!
exception
&&
!
d_is_undef_i
;
w_store_o
<=
d_is_store_i
&&
!
x_kill_i
&&
d_valid_i
&&
!
exception
&&
!
d_is_undef_i
;
w_rd_source_o
<=
d_rd_source_i
;
w_fun_o
<=
d_fun_i
;
...
...
tb/isa-testsuite/Manifest.py
View file @
9016844b
sim_tool
=
"modelsim"
top_module
=
"main"
syn_device
=
"xc6slx150t"
sim_top
=
"main"
action
=
"simulation"
target
=
"xilinx"
include_dirs
=
[
"../../rtl"
]
...
...
tb/isa-testsuite/main.sv
View file @
9016844b
...
...
@@ -18,33 +18,37 @@
*/
`include
"rv_defs.v"
`define
URV_PLATFORM_SPARTAN6
`include
"urv_defs.v"
`timescale
1
ns
/
1
ps
module
main
;
module
main
;
reg
clk
=
0
;
reg
rst
=
1
;
wire
[
31
:
0
]
im_addr
;
reg
[
31
:
0
]
im_data
;
reg
im_valid
;
reg
[
31
:
0
]
im_data
;
reg
im_valid
;
wire
[
31
:
0
]
dm_addr
;
wire
[
31
:
0
]
dm_data_s
;
reg
[
31
:
0
]
dm_data_l
;
reg
[
31
:
0
]
dm_data_l
;
wire
[
3
:
0
]
dm_data_select
;
wire
dm_write
;
reg
dm_valid_l
=
1
;
reg
dm_ready
;
reg
dm_ready
;
wire
irq
=
0
;
localparam
int
mem_size
=
16384
;
reg
[
31
:
0
]
mem
[
0
:
mem_size
-
1
]
;
// loads memory contents from a text file
task
automatic
load_ram
(
string
filename
)
;
int
f
=
$
fopen
(
filename
,
"r"
)
;
int
n
,
i
;
...
...
@@ -55,8 +59,6 @@ module main;
$
stop
;
end
while
(
!
$
feof
(
f
))
begin
int
addr
,
data
;
...
...
@@ -73,8 +75,7 @@ module main;
int
seed
;
// instruction and data memories
always
@
(
posedge
clk
)
begin
if
(
$
dist_uniform
(
seed
,
0
,
100
)
<=
100
)
begin
...
...
@@ -82,8 +83,6 @@ module main;
im_valid
<=
1
;
end
else
im_valid
<=
0
;
if
(
dm_write
&&
dm_data_select
[
0
])
mem
[(
dm_addr
/
4
)
%
mem_size
][
7
:
0
]
<=
dm_data_s
[
7
:
0
]
;
...
...
@@ -94,24 +93,17 @@ module main;
if
(
dm_write
&&
dm_data_select
[
3
])
mem
[(
dm_addr
/
4
)
%
mem_size
][
31
:
24
]
<=
dm_data_s
[
31
:
24
]
;
// dm_data_l <= mem[(dm_addr/4) % mem_size];
end
// always@ (posedge clk)
always
@
(
posedge
clk
)
begin
dm_ready
<=
1'b1
;
// $dist_uniform(seed, 0, 100 ) <= 50;
dm_data_l
<=
mem
[(
dm_addr
/
4
)
%
mem_size
]
;
end
end
rv_cpu
DUT
u
rv_cpu
DUT
(
.
clk_i
(
clk
)
,
.
rst_i
(
rst
)
,
...
...
@@ -145,7 +137,7 @@ module main;
string
tests
[$]
;
string
test_dir
=
"../../sw/testsuite/isa"
;
// load all tests listed in the file
int
f
=
$
fopen
(
{
test_dir
,
"/tests.lst"
}
,
"r"
)
;
int
n
,
i
;
...
...
@@ -157,8 +149,6 @@ module main;
$
fscanf
(
f
,
"%s"
,
fname
)
;
tests
.
push_back
(
fname
)
;
end
...
...
@@ -180,21 +170,20 @@ module main;
end
// initial begin
// report test completeness/status. The test applets indicate this by writing predefined
// memory locations.
always
@
(
posedge
clk
)
if
(
dm_write
)
begin
if
(
dm_addr
==
'h100000
)
begin
// $display("\n ****** TX '%c' \n", dm_data_s[7:0]) ;
// $fwrite(f_exec_log,"\n ****** TX '%c' \n", dm_data_s[7:0]) ;
$
write
(
"%c"
,
dm_data_s
[
7
:
0
])
;
$
fwrite
(
f_console
,
"%c"
,
dm_data_s
[
7
:
0
])
;
$
fflush
(
f_console
)
;
end
else
if
(
dm_addr
==
'h100004
)
begin
// $display("Test complete." );
test_complete
=
1
;
end
end
...
...
tb/isa-testsuite/wave.do
View file @
9016844b
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