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urv-core
Commits
8680d785
Commit
8680d785
authored
May 28, 2015
by
Tomasz Wlostowski
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Plain Diff
fixed WB stall
parent
40e55b9a
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5 changed files
with
11 additions
and
9 deletions
+11
-9
Manifest.py
rtl/Manifest.py
+1
-2
rv_exec.v
rtl/rv_exec.v
+1
-1
rv_fetch.v
rtl/rv_fetch.v
+1
-1
rv_writeback.v
rtl/rv_writeback.v
+2
-2
xrv_core.vhd
rtl/xrv_core.vhd
+6
-3
No files found.
rtl/Manifest.py
View file @
8680d785
...
...
@@ -6,8 +6,7 @@ action = "simulation"
target
=
"xilinx"
include_dirs
=
[
"."
]
files
=
[
"main.sv"
,
"rv_cpu.v"
,
files
=
[
"rv_cpu.v"
,
"rv_exec.v"
,
"rv_fetch.v"
,
"rv_predecode.v"
,
...
...
rtl/rv_exec.v
View file @
8680d785
...
...
@@ -293,7 +293,7 @@ module rv_exec
f_branch_target_o
<=
0
;
f_branch_take
<=
0
;
w_rd_write_o
<=
0
;
w_rd_o
<=
0
;
//
w_rd_o <= 0;
w_fun_o
<=
0
;
w_load_o
<=
0
;
w_store_o
<=
0
;
...
...
rtl/rv_fetch.v
View file @
8680d785
...
...
@@ -64,7 +64,7 @@ module rv_fetch
always
@
(
posedge
clk_i
)
if
(
rst_i
)
begin
pc
<=
-
4
;
pc
<=
0
;
ir
<=
0
;
f_valid_o
<=
0
;
rst_d
<=
0
;
...
...
rtl/rv_writeback.v
View file @
8680d785
...
...
@@ -129,11 +129,11 @@ module rv_writeback
end
assign
rf_rd_value_o
=
(
x_load_i
?
load_value
:
x_rd_value_i
)
;
assign
rf_rd_value_o
=
(
x_load_i
||
pending_load
?
load_value
:
x_rd_value_i
)
;
assign
rf_rd_o
=
(
x_rd_i
)
;
assign
rf_rd_write_o
=
!
interlock_d
&&
(
w_stall_i
?
1'b0
:
((
x_load_i
||
pending_load
)
&&
dm_load_done_i
?
1'b1
:
x_rd_write_i
))
;
assign
w_stall_req_o
=
(
pending_load
&&
!
dm_load_done_i
)
||
(
pending_store
&&
!
dm_store_done_i
)
||
(
interlock
&&
!
interlock_d
)
;
assign
w_stall_req_o
=
(
(
x_load_i
||
pending_load
)
&&
!
dm_load_done_i
)
||
((
x_store_i
||
pending_store
)
&&
!
dm_store_done_i
)
||
(
interlock
&&
!
interlock_d
)
;
...
...
rtl/xrv_core.vhd
View file @
8680d785
...
...
@@ -74,7 +74,8 @@ architecture wrapper of xrv_core is
);
end
component
;
signal
cpu_rst
:
std_logic
;
signal
cpu_rst
,
cpu_rst_d
:
std_logic
;
signal
im_addr
:
std_logic_vector
(
31
downto
0
);
signal
im_data
:
std_logic_vector
(
31
downto
0
);
signal
im_valid
:
std_logic
;
...
...
@@ -234,7 +235,7 @@ begin
rst_n_i
=>
rst_n_i
,
clka_i
=>
clk_sys_i
,
wea_i
=>
ha_im_write
,
wea_i
=>
'0'
,
--
ha_im_write,
aa_i
=>
im_addr_muxed
(
c_mem_address_bits
+
1
downto
2
),
da_i
=>
ha_im_wdata
,
qa_o
=>
im_data
,
...
...
@@ -252,8 +253,10 @@ begin
if
rising_edge
(
clk_sys_i
)
then
if
(
cpu_rst
=
'1'
)
then
im_valid
<=
'0'
;
cpu_rst_d
<=
'1'
;
else
im_valid
<=
not
ha_im_access
;
cpu_rst_d
<=
cpu_rst
;
im_valid
<=
not
ha_im_access
and
(
not
cpu_rst_d
);
end
if
;
end
if
;
end
process
;
...
...
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