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urv-core
Commit 79a000cb authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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added wait states to the I/D interface. not tested yet

parent 8d0fb7a5
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Showing with 154 additions and 139 deletions
main.sv
View file @ 79a000cb
...@@ -41,7 +41,9 @@ module main; ...@@ -41,7 +41,9 @@ module main;
reg [31:0] dm_data_l; reg [31:0] dm_data_l;
wire [3:0] dm_data_select; wire [3:0] dm_data_select;
wire dm_write; wire dm_write;
reg dm_valid_l = 0; reg dm_valid_l = 1;
reg dm_ready;
localparam int mem_size = 16384; localparam int mem_size = 16384;
...@@ -88,21 +90,24 @@ module main; ...@@ -88,21 +90,24 @@ module main;
mem [(dm_addr / 4) % mem_size][23:16] <= dm_data_s[23:16]; mem [(dm_addr / 4) % mem_size][23:16] <= dm_data_s[23:16];
if(dm_write && dm_data_select[3]) if(dm_write && dm_data_select[3])
mem [(dm_addr / 4) % mem_size][31:24] <= dm_data_s[31:24]; mem [(dm_addr / 4) % mem_size][31:24] <= dm_data_s[31:24];
if( $dist_uniform(seed, 0, 100 ) <= 50) begin
dm_data_l <= mem[(dm_addr/4) % mem_size];
dm_valid_l <= 1;
end else begin
dm_data_l <= 32'hx;
dm_valid_l <= 0;
end
// dm_data_l <= mem[(dm_addr/4) % mem_size]; // dm_data_l <= mem[(dm_addr/4) % mem_size];
end end // always@ (posedge clk)
always@(posedge clk)
begin
dm_ready <= 1'b1; // $dist_uniform(seed, 0, 100 ) <= 50;
dm_data_l <= mem[(dm_addr/4) % mem_size];
end
rv_cpu DUT rv_cpu DUT
( (
...@@ -119,8 +124,11 @@ module main; ...@@ -119,8 +124,11 @@ module main;
.dm_data_s_o(dm_data_s), .dm_data_s_o(dm_data_s),
.dm_data_l_i(dm_data_l), .dm_data_l_i(dm_data_l),
.dm_data_select_o(dm_data_select), .dm_data_select_o(dm_data_select),
.dm_write_o(dm_write), .dm_store_o(dm_write),
.dm_valid_l_i(dm_valid_l) .dm_load_o(),
.dm_store_done_i(1'b1),
.dm_load_done_i(1'b1),
.dm_ready_i(dm_ready)
); );
always #5ns clk <= ~clk; always #5ns clk <= ~clk;
......
rv_cpu.v
View file @ 79a000cb
...@@ -37,9 +37,12 @@ module rv_cpu ...@@ -37,9 +37,12 @@ module rv_cpu
output [31:0] dm_data_s_o, output [31:0] dm_data_s_o,
input [31:0] dm_data_l_i, input [31:0] dm_data_l_i,
output [3:0] dm_data_select_o, output [3:0] dm_data_select_o,
output dm_write_o, input dm_ready_i,
input dm_busy_s_i,
input dm_valid_l_i output dm_store_o,
output dm_load_o,
input dm_load_done_i,
input dm_store_done_i
); );
wire f_stall; wire f_stall;
...@@ -96,6 +99,8 @@ module rv_cpu ...@@ -96,6 +99,8 @@ module rv_cpu
.rst_i(rst_i), .rst_i(rst_i),
.im_data_i(im_data_i), .im_data_i(im_data_i),
.f_stall_i(f_stall),
.f_ir_i(f2d_ir), .f_ir_i(f2d_ir),
.f_pc_i(f2d_pc), .f_pc_i(f2d_pc),
...@@ -156,6 +161,8 @@ module rv_cpu ...@@ -156,6 +161,8 @@ module rv_cpu
wire [31:0] x2w_dm_addr; wire [31:0] x2w_dm_addr;
wire x2w_rd_write; wire x2w_rd_write;
wire [2:0] x2w_fun; wire [2:0] x2w_fun;
wire x2w_store;
rv_exec execute rv_exec execute
...@@ -190,6 +197,7 @@ module rv_cpu ...@@ -190,6 +197,7 @@ module rv_cpu
// Writeback stage I/F // Writeback stage I/F
.w_fun_o(x2w_fun), .w_fun_o(x2w_fun),
.w_load_o(x2w_load), .w_load_o(x2w_load),
.w_store_o(x2w_store),
.w_dm_addr_o(x2w_dm_addr), .w_dm_addr_o(x2w_dm_addr),
.w_rd_o(x2w_rd), .w_rd_o(x2w_rd),
...@@ -199,7 +207,9 @@ module rv_cpu ...@@ -199,7 +207,9 @@ module rv_cpu
.dm_addr_o(dm_addr_o), .dm_addr_o(dm_addr_o),
.dm_data_s_o(dm_data_s_o), .dm_data_s_o(dm_data_s_o),
.dm_data_select_o(dm_data_select_o), .dm_data_select_o(dm_data_select_o),
.dm_write_o(dm_write_o) .dm_store_o(dm_store_o),
.dm_load_o(dm_load_o),
.dm_ready_i(dm_ready_i)
); );
wire w_stall_req; wire w_stall_req;
...@@ -215,15 +225,18 @@ module rv_cpu ...@@ -215,15 +225,18 @@ module rv_cpu
.x_fun_i(x2w_fun), .x_fun_i(x2w_fun),
.x_load_i(x2w_load), .x_load_i(x2w_load),
.x_store_i(x2w_store),
.x_rd_i(x2w_rd), .x_rd_i(x2w_rd),
.x_rd_value_i(x2w_rd_value), .x_rd_value_i(x2w_rd_value),
.x_rd_write_i(x2w_rd_write), .x_rd_write_i(x2w_rd_write),
.x_dm_addr_i(x2w_dm_addr), .x_dm_addr_i(x2w_dm_addr),
.dm_data_l_i(dm_data_l_i), .dm_data_l_i(dm_data_l_i),
.dm_valid_l_i(dm_valid_l_i), .dm_load_done_i(dm_load_done_i),
.dm_store_done_i(dm_store_done_i),
.rf_rd_value_o(rf_rd_value), .rf_rd_value_o(rf_rd_value),
.rf_rd_o(rf_rd), .rf_rd_o(rf_rd),
.rf_rd_write_o(rf_rd_write) .rf_rd_write_o(rf_rd_write)
......
rv_exec.v
View file @ 79a000cb
...@@ -55,6 +55,7 @@ module rv_exec ...@@ -55,6 +55,7 @@ module rv_exec
// Writeback stage I/F // Writeback stage I/F
output reg [2:0 ] w_fun_o, output reg [2:0 ] w_fun_o,
output reg w_load_o, output reg w_load_o,
output reg w_store_o,
output reg [4:0] w_rd_o, output reg [4:0] w_rd_o,
output reg [31:0] w_rd_value_o, output reg [31:0] w_rd_value_o,
...@@ -65,8 +66,9 @@ module rv_exec ...@@ -65,8 +66,9 @@ module rv_exec
output [31:0] dm_addr_o, output [31:0] dm_addr_o,
output [31:0] dm_data_s_o, output [31:0] dm_data_s_o,
output [3:0] dm_data_select_o, output [3:0] dm_data_select_o,
// input [31:0] dm_data_l_i, output dm_store_o,
output dm_write_o output dm_load_o,
input dm_ready_i
); );
wire [31:0] rs1, rs2; wire [31:0] rs1, rs2;
...@@ -84,7 +86,6 @@ module rv_exec ...@@ -84,7 +86,6 @@ module rv_exec
reg [31:0] branch_target; reg [31:0] branch_target;
reg [31:0] dm_addr, dm_data_s, dm_select_s; reg [31:0] dm_addr, dm_data_s, dm_select_s;
reg dm_write_s;
reg rd_write; reg rd_write;
...@@ -237,21 +238,9 @@ module rv_exec ...@@ -237,21 +238,9 @@ module rv_exec
shifter_req_d0 <= shifter_req; shifter_req_d0 <= shifter_req;
wire shifter_stall_req = shifter_req && !shifter_req_d0; wire shifter_stall_req = shifter_req && !shifter_req_d0;
// && !shifter_req_d0;
/* always@(posedge clk_i)
if(shifter_req)
$display("%08x: shifter op %x fun %x %x op1 %x op2 %x", d_pc_i, d_opcode_i, d_fun_i, d_shifter_sign_i, alu_op1, alu_op2);
always@(posedge clk_i)
if(shifter_req_d0)
$display("%08x: shifter result %x", d_pc_i, shifter_result);
*/
// rdest write value // rdest write value
always@* always@*
begin begin
case (d_opcode_i) case (d_opcode_i)
`OPC_OP_IMM, `OPC_OP, `OPC_JAL, `OPC_JALR, `OPC_LUI, `OPC_AUIPC: `OPC_OP_IMM, `OPC_OP, `OPC_JAL, `OPC_JALR, `OPC_LUI, `OPC_AUIPC:
...@@ -260,36 +249,14 @@ module rv_exec ...@@ -260,36 +249,14 @@ module rv_exec
rd_write <= 1; rd_write <= 1;
end end
/* `OPC_JAL, `OPC_JALR:
begin
rd_value <= d_pc_i + 4;
rd_write <= 1;
end
`OPC_LUI:
begin
rd_value <= { d_imm_u_i[31:12] , 12'h0 };
rd_write <= 1;
end
`OPC_AUIPC:
begin
rd_value <= d_pc_i + { d_imm_u_i[31:12], 12'h0 };
rd_write <= 1;
end
*/
default: default:
begin begin
rd_value <= 32'hx; rd_value <= 32'hx;
rd_write <= 0; rd_write <= 0;
end end
endcase endcase
end end
// generate load/store address // generate load/store address
always@* always@*
begin begin
...@@ -304,7 +271,7 @@ module rv_exec ...@@ -304,7 +271,7 @@ module rv_exec
// generate store value/select // generate store value/select
always@* always@*
begin begin
case (d_fun_i) case (d_fun_i)
`LDST_B: `LDST_B:
begin begin
dm_data_s <= { rs2[7:0], rs2[7:0], rs2[7:0], rs2[7:0] }; dm_data_s <= { rs2[7:0], rs2[7:0], rs2[7:0], rs2[7:0] };
...@@ -341,28 +308,27 @@ module rv_exec ...@@ -341,28 +308,27 @@ module rv_exec
//branch decision //branch decision
always@* always@*
case (d_opcode_i) case (d_opcode_i)
`OPC_JAL, `OPC_JALR: `OPC_JAL, `OPC_JALR:
branch_take <= 1; branch_take <= 1;
`OPC_BRANCH: `OPC_BRANCH:
branch_take <= branch_condition_met; branch_take <= branch_condition_met;
default: default:
branch_take <= 0; branch_take <= 0;
endcase // case (d_opcode_i) endcase // case (d_opcode_i)
// generate store write // generate load/store requests
always@*
begin
dm_write_s <= ( (d_opcode_i == `OPC_STORE) && !x_stall_i && d_valid_i);
end
assign dm_addr_o = dm_addr; assign dm_addr_o = dm_addr;
assign dm_data_s_o = dm_data_s; assign dm_data_s_o = dm_data_s;
assign dm_data_select_o = dm_select_s; assign dm_data_select_o = dm_select_s;
assign dm_write_o = dm_write_s;
wire is_load = (d_opcode_i == `OPC_LOAD ? 1: 0) && d_valid_i && !x_kill_i;
wire is_store = (d_opcode_i == `OPC_STORE ? 1: 0) && d_valid_i && !x_kill_i;
assign dm_load_o = is_load;
assign dm_store_o = is_store;
always@(posedge clk_i) always@(posedge clk_i)
if (rst_i) begin if (rst_i) begin
...@@ -372,8 +338,10 @@ module rv_exec ...@@ -372,8 +338,10 @@ module rv_exec
w_rd_o <= 0; w_rd_o <= 0;
w_fun_o <= 0; w_fun_o <= 0;
w_load_o <= 0; w_load_o <= 0;
w_store_o <= 0;
w_dm_addr_o <= 0; w_dm_addr_o <= 0;
end else if (!x_stall_i) begin end else if (!x_stall_i) begin
f_branch_target_o <= branch_target; f_branch_target_o <= branch_target;
f_branch_take_o <= branch_take && !x_kill_i && d_valid_i; f_branch_take_o <= branch_take && !x_kill_i && d_valid_i;
...@@ -386,16 +354,19 @@ module rv_exec ...@@ -386,16 +354,19 @@ module rv_exec
w_rd_write_o <= rd_write && !x_kill_i && d_valid_i; w_rd_write_o <= rd_write && !x_kill_i && d_valid_i;
w_fun_o <= d_fun_i; w_fun_o <= d_fun_i;
w_load_o <= (d_opcode_i == `OPC_LOAD ? 1: 0) && d_valid_i && !x_kill_i; w_load_o <= is_load;
w_store_o <= is_store;
w_dm_addr_o <= dm_addr; w_dm_addr_o <= dm_addr;
end else begin // if (!x_stall_i) end else begin // if (!x_stall_i)
f_branch_take_o <= 0; f_branch_take_o <= 0;
w_rd_write_o <= 0; w_rd_write_o <= 0;
w_load_o <= 0; w_load_o <= 0;
w_store_o <= 0;
end end
assign x_stall_req_o = shifter_stall_req; assign x_stall_req_o = shifter_stall_req || ((is_store || is_load) && !dm_ready_i);
endmodule endmodule
......
rv_predecode.v
View file @ 79a000cb
...@@ -25,42 +25,44 @@ ...@@ -25,42 +25,44 @@
module rv_predecode module rv_predecode
( (
input clk_i, input clk_i,
input rst_i, input rst_i,
input [31:0] im_data_i, input [31:0] im_data_i,
input [31:0] f_ir_i,
input [31:0] f_pc_i,
input f_stall_i,
input [31:0] f_ir_i,
input [31:0] f_pc_i,
output [31:0] x_pc_o, output [31:0] x_pc_o,
output [4:0] rf_rs1_o, output [4:0] rf_rs1_o,
output [4:0] rf_rs2_o, output [4:0] rf_rs2_o,
output [4:0] x_rs1_o, output [4:0] x_rs1_o,
output [4:0] x_rs2_o, output [4:0] x_rs2_o,
output [4:0] x_rd_o, output [4:0] x_rd_o,
output [4:0] x_shamt_o, output [4:0] x_shamt_o,
output reg [2:0] x_fun_o, output reg [2:0] x_fun_o,
output [4:0] x_opcode_o, output [4:0] x_opcode_o,
output x_shifter_sign_o, output x_shifter_sign_o,
output [31:0] x_imm_i_o, output [31:0] x_imm_i_o,
output [31:0] x_imm_s_o, output [31:0] x_imm_s_o,
output [31:0] x_imm_b_o, output [31:0] x_imm_b_o,
output [31:0] x_imm_u_o, output [31:0] x_imm_u_o,
output [31:0] x_imm_j_o output [31:0] x_imm_j_o
); );
wire [4:0] f_opcode = f_ir_i[6:2]; wire [4:0] f_opcode = f_ir_i[6:2];
assign rf_rs1_o = im_data_i [19:15]; assign rf_rs1_o = f_stall_i ? f_ir_i[19:15] : im_data_i [19:15];
assign rf_rs2_o = im_data_i [24:20]; assign rf_rs2_o = f_stall_i ? f_ir_i[24:20] : im_data_i [24:20];
assign x_rs1_o = f_ir_i [19:15]; assign x_rs1_o = f_ir_i [19:15];
......
rv_writeback.v
View file @ 79a000cb
...@@ -31,9 +31,10 @@ module rv_writeback ...@@ -31,9 +31,10 @@ module rv_writeback
output w_stall_req_o, output w_stall_req_o,
input [2:0] x_fun_i, input [2:0] x_fun_i,
input x_load_i, input x_load_i,
input x_store_i,
input [31:0] x_dm_addr_i, input [31:0] x_dm_addr_i,
input [4:0] x_rd_i, input [4:0] x_rd_i,
...@@ -41,7 +42,8 @@ module rv_writeback ...@@ -41,7 +42,8 @@ module rv_writeback
input x_rd_write_i, input x_rd_write_i,
input [31:0] dm_data_l_i, input [31:0] dm_data_l_i,
input dm_valid_l_i, input dm_load_done_i,
input dm_store_done_i,
output [31:0] rf_rd_value_o, output [31:0] rf_rd_value_o,
output [4:0] rf_rd_o, output [4:0] rf_rd_o,
...@@ -96,8 +98,8 @@ module rv_writeback ...@@ -96,8 +98,8 @@ module rv_writeback
assign rf_rd_value_o = (x_load_i ? load_value : x_rd_value_i ); assign rf_rd_value_o = (x_load_i ? load_value : x_rd_value_i );
assign rf_rd_o = (x_rd_i); assign rf_rd_o = (x_rd_i);
assign rf_rd_write_o = (w_stall_i ? 1'b0 : (x_load_i && dm_valid_l_i ? 1'b1 : x_rd_write_i )); assign rf_rd_write_o = (w_stall_i ? 1'b0 : (x_load_i && dm_load_done_i ? 1'b1 : x_rd_write_i ));
assign w_stall_req_o = (x_load_i && !dm_valid_l_i); assign w_stall_req_o = (x_load_i && !dm_load_done_i) || (x_store_i && !dm_store_done_i);
endmodule // rv_writeback endmodule // rv_writeback
wave.do
View file @ 79a000cb
...@@ -2,35 +2,38 @@ onerror {resume} ...@@ -2,35 +2,38 @@ onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/clk_i add wave -noupdate /main/DUT/clk_i
add wave -noupdate /main/DUT/rst_i add wave -noupdate /main/DUT/rst_i
add wave -noupdate -group cpu /main/DUT/clk_i add wave -noupdate -expand -group cpu /main/DUT/clk_i
add wave -noupdate -group cpu /main/DUT/rst_i add wave -noupdate -expand -group cpu /main/DUT/im_data_i
add wave -noupdate -group cpu /main/DUT/im_addr_o add wave -noupdate -expand -group cpu /main/DUT/im_valid_i
add wave -noupdate -group cpu /main/DUT/im_data_i add wave -noupdate -expand -group cpu /main/DUT/dm_addr_o
add wave -noupdate -group cpu /main/DUT/im_valid_i add wave -noupdate -expand -group cpu /main/DUT/dm_data_s_o
add wave -noupdate -group cpu /main/DUT/dm_addr_o add wave -noupdate -expand -group cpu /main/DUT/dm_data_l_i
add wave -noupdate -group cpu /main/DUT/dm_data_s_o add wave -noupdate -expand -group cpu /main/DUT/dm_data_select_o
add wave -noupdate -group cpu /main/DUT/dm_data_l_i add wave -noupdate -expand -group cpu /main/DUT/dm_ready_i
add wave -noupdate -group cpu /main/DUT/dm_data_select_o add wave -noupdate -expand -group cpu /main/DUT/dm_store_o
add wave -noupdate -group cpu /main/DUT/dm_write_o add wave -noupdate -expand -group cpu /main/DUT/dm_load_o
add wave -noupdate -group cpu /main/DUT/f_stall add wave -noupdate -expand -group cpu /main/DUT/dm_load_done_i
add wave -noupdate -group cpu /main/DUT/f2d_pc add wave -noupdate -expand -group cpu /main/DUT/dm_store_done_i
add wave -noupdate -group cpu /main/DUT/f2d_ir add wave -noupdate -expand -group cpu /main/DUT/rst_i
add wave -noupdate -group cpu /main/DUT/f2d_ir_valid add wave -noupdate -expand -group cpu /main/DUT/f_stall
add wave -noupdate -group cpu /main/DUT/x2f_pc_bra add wave -noupdate -expand -group cpu /main/DUT/f2d_pc
add wave -noupdate -group cpu /main/DUT/x2f_bra add wave -noupdate -expand -group cpu /main/DUT/f2d_ir
add wave -noupdate -group cpu /main/DUT/d2x_pc add wave -noupdate -expand -group cpu /main/DUT/f2d_ir_valid
add wave -noupdate -group cpu /main/DUT/rf_rs2 add wave -noupdate -expand -group cpu /main/DUT/x2f_pc_bra
add wave -noupdate -group cpu /main/DUT/rf_rs1 add wave -noupdate -expand -group cpu /main/DUT/x2f_bra
add wave -noupdate -group cpu /main/DUT/d2x_rd add wave -noupdate -expand -group cpu /main/DUT/d2x_pc
add wave -noupdate -group cpu /main/DUT/d2x_shamt add wave -noupdate -expand -group cpu /main/DUT/rf_rs2
add wave -noupdate -group cpu /main/DUT/d2x_fun add wave -noupdate -expand -group cpu /main/DUT/rf_rs1
add wave -noupdate -group cpu /main/DUT/d2x_opcode add wave -noupdate -expand -group cpu /main/DUT/d2x_rd
add wave -noupdate -group cpu /main/DUT/d2x_shifter_sign add wave -noupdate -expand -group cpu /main/DUT/d2x_shamt
add wave -noupdate -group cpu /main/DUT/d2x_imm_i add wave -noupdate -expand -group cpu /main/DUT/d2x_fun
add wave -noupdate -group cpu /main/DUT/d2x_imm_s add wave -noupdate -expand -group cpu /main/DUT/d2x_opcode
add wave -noupdate -group cpu /main/DUT/d2x_imm_b add wave -noupdate -expand -group cpu /main/DUT/d2x_shifter_sign
add wave -noupdate -group cpu /main/DUT/d2x_imm_u add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_i
add wave -noupdate -group cpu /main/DUT/d2x_imm_j add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_s
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_b
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_u
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_j
add wave -noupdate -expand -group fetch /main/DUT/fetch/clk_i add wave -noupdate -expand -group fetch /main/DUT/fetch/clk_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/rst_i add wave -noupdate -expand -group fetch /main/DUT/fetch/rst_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/im_addr_o add wave -noupdate -expand -group fetch /main/DUT/fetch/im_addr_o
...@@ -104,18 +107,15 @@ add wave -noupdate -expand -group shifter /main/DUT/execute/shifter/shift_1 ...@@ -104,18 +107,15 @@ add wave -noupdate -expand -group shifter /main/DUT/execute/shifter/shift_1
add wave -noupdate -expand -group shifter /main/DUT/execute/shifter/shift_post add wave -noupdate -expand -group shifter /main/DUT/execute/shifter/shift_post
add wave -noupdate -expand -group execute /main/DUT/execute/clk_i add wave -noupdate -expand -group execute /main/DUT/execute/clk_i
add wave -noupdate -expand -group execute /main/DUT/execute/rst_i add wave -noupdate -expand -group execute /main/DUT/execute/rst_i
add wave -noupdate -expand -group execute /main/DUT/execute/x_kill_i
add wave -noupdate -expand -group execute /main/DUT/execute/x_stall_i add wave -noupdate -expand -group execute /main/DUT/execute/x_stall_i
add wave -noupdate -expand -group execute /main/DUT/execute/x_kill_i
add wave -noupdate -expand -group execute /main/DUT/execute/x_stall_req_o add wave -noupdate -expand -group execute /main/DUT/execute/x_stall_req_o
add wave -noupdate -expand -group execute /main/DUT/execute/d_valid_i
add wave -noupdate -expand -group execute /main/DUT/execute/shifter_req
add wave -noupdate -expand -group execute /main/DUT/execute/shifter_req_d0
add wave -noupdate -expand -group execute /main/DUT/execute/shifter_stall_req
add wave -noupdate -expand -group execute /main/DUT/execute/d_pc_i add wave -noupdate -expand -group execute /main/DUT/execute/d_pc_i
add wave -noupdate -expand -group execute /main/DUT/execute/d_rd_i add wave -noupdate -expand -group execute /main/DUT/execute/d_rd_i
add wave -noupdate -expand -group execute /main/DUT/execute/d_fun_i add wave -noupdate -expand -group execute /main/DUT/execute/d_fun_i
add wave -noupdate -expand -group execute /main/DUT/execute/rf_rs1_value_i add wave -noupdate -expand -group execute /main/DUT/execute/rf_rs1_value_i
add wave -noupdate -expand -group execute /main/DUT/execute/rf_rs2_value_i add wave -noupdate -expand -group execute /main/DUT/execute/rf_rs2_value_i
add wave -noupdate -expand -group execute /main/DUT/execute/d_valid_i
add wave -noupdate -expand -group execute /main/DUT/execute/d_opcode_i add wave -noupdate -expand -group execute /main/DUT/execute/d_opcode_i
add wave -noupdate -expand -group execute /main/DUT/execute/d_shifter_sign_i add wave -noupdate -expand -group execute /main/DUT/execute/d_shifter_sign_i
add wave -noupdate -expand -group execute /main/DUT/execute/d_imm_i_i add wave -noupdate -expand -group execute /main/DUT/execute/d_imm_i_i
...@@ -127,13 +127,17 @@ add wave -noupdate -expand -group execute /main/DUT/execute/f_branch_target_o ...@@ -127,13 +127,17 @@ add wave -noupdate -expand -group execute /main/DUT/execute/f_branch_target_o
add wave -noupdate -expand -group execute /main/DUT/execute/f_branch_take_o add wave -noupdate -expand -group execute /main/DUT/execute/f_branch_take_o
add wave -noupdate -expand -group execute /main/DUT/execute/w_fun_o add wave -noupdate -expand -group execute /main/DUT/execute/w_fun_o
add wave -noupdate -expand -group execute /main/DUT/execute/w_load_o add wave -noupdate -expand -group execute /main/DUT/execute/w_load_o
add wave -noupdate -expand -group execute /main/DUT/execute/w_store_o
add wave -noupdate -expand -group execute /main/DUT/execute/w_rd_o add wave -noupdate -expand -group execute /main/DUT/execute/w_rd_o
add wave -noupdate -expand -group execute /main/DUT/execute/w_rd_value_o add wave -noupdate -expand -group execute /main/DUT/execute/w_rd_value_o
add wave -noupdate -expand -group execute /main/DUT/execute/w_rd_write_o add wave -noupdate -expand -group execute /main/DUT/execute/w_rd_write_o
add wave -noupdate -expand -group execute /main/DUT/execute/w_dm_addr_o
add wave -noupdate -expand -group execute /main/DUT/execute/dm_addr_o add wave -noupdate -expand -group execute /main/DUT/execute/dm_addr_o
add wave -noupdate -expand -group execute /main/DUT/execute/dm_data_s_o add wave -noupdate -expand -group execute /main/DUT/execute/dm_data_s_o
add wave -noupdate -expand -group execute /main/DUT/execute/dm_data_select_o add wave -noupdate -expand -group execute /main/DUT/execute/dm_data_select_o
add wave -noupdate -expand -group execute /main/DUT/execute/dm_write_o add wave -noupdate -expand -group execute /main/DUT/execute/dm_store_o
add wave -noupdate -expand -group execute /main/DUT/execute/dm_load_o
add wave -noupdate -expand -group execute /main/DUT/execute/dm_ready_i
add wave -noupdate -expand -group execute /main/DUT/execute/rs1 add wave -noupdate -expand -group execute /main/DUT/execute/rs1
add wave -noupdate -expand -group execute /main/DUT/execute/rs2 add wave -noupdate -expand -group execute /main/DUT/execute/rs2
add wave -noupdate -expand -group execute /main/DUT/execute/alu_op1 add wave -noupdate -expand -group execute /main/DUT/execute/alu_op1
...@@ -141,29 +145,44 @@ add wave -noupdate -expand -group execute /main/DUT/execute/alu_op2 ...@@ -141,29 +145,44 @@ add wave -noupdate -expand -group execute /main/DUT/execute/alu_op2
add wave -noupdate -expand -group execute /main/DUT/execute/alu_result add wave -noupdate -expand -group execute /main/DUT/execute/alu_result
add wave -noupdate -expand -group execute /main/DUT/execute/rd_value add wave -noupdate -expand -group execute /main/DUT/execute/rd_value
add wave -noupdate -expand -group execute /main/DUT/execute/branch_take add wave -noupdate -expand -group execute /main/DUT/execute/branch_take
add wave -noupdate -expand -group execute /main/DUT/execute/branch_condition_met
add wave -noupdate -expand -group execute /main/DUT/execute/branch_target add wave -noupdate -expand -group execute /main/DUT/execute/branch_target
add wave -noupdate -expand -group execute /main/DUT/execute/dm_addr add wave -noupdate -expand -group execute /main/DUT/execute/dm_addr
add wave -noupdate -expand -group execute /main/DUT/execute/dm_data_s add wave -noupdate -expand -group execute /main/DUT/execute/dm_data_s
add wave -noupdate -expand -group execute /main/DUT/execute/dm_select_s add wave -noupdate -expand -group execute /main/DUT/execute/dm_select_s
add wave -noupdate -expand -group execute /main/DUT/execute/dm_write_s
add wave -noupdate -expand -group execute /main/DUT/execute/rd_write add wave -noupdate -expand -group execute /main/DUT/execute/rd_write
add wave -noupdate -expand -group execute /main/DUT/execute/cmp_sign_ext
add wave -noupdate -expand -group execute /main/DUT/execute/cmp_op1
add wave -noupdate -expand -group execute /main/DUT/execute/cmp_op2
add wave -noupdate -expand -group execute /main/DUT/execute/cmp_equal
add wave -noupdate -expand -group execute /main/DUT/execute/cmp_lt
add wave -noupdate -expand -group execute /main/DUT/execute/is_subtract
add wave -noupdate -expand -group execute /main/DUT/execute/shifter_result
add wave -noupdate -expand -group execute /main/DUT/execute/shifter_req_d0
add wave -noupdate -expand -group execute /main/DUT/execute/shifter_req
add wave -noupdate -expand -group execute /main/DUT/execute/shifter_stall_req
add wave -noupdate -expand -group execute /main/DUT/execute/is_load
add wave -noupdate -expand -group execute /main/DUT/execute/is_store
add wave -noupdate -expand -group writeback /main/DUT/writeback/clk_i add wave -noupdate -expand -group writeback /main/DUT/writeback/clk_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/rst_i add wave -noupdate -expand -group writeback /main/DUT/writeback/rst_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/w_stall_i add wave -noupdate -expand -group writeback /main/DUT/writeback/w_stall_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/w_stall_req_o add wave -noupdate -expand -group writeback /main/DUT/writeback/w_stall_req_o
add wave -noupdate -expand -group writeback /main/DUT/writeback/x_fun_i add wave -noupdate -expand -group writeback /main/DUT/writeback/x_fun_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/x_load_i add wave -noupdate -expand -group writeback /main/DUT/writeback/x_load_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/x_store_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/x_dm_addr_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/x_rd_i add wave -noupdate -expand -group writeback /main/DUT/writeback/x_rd_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/x_rd_value_i add wave -noupdate -expand -group writeback /main/DUT/writeback/x_rd_value_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/x_rd_write_i add wave -noupdate -expand -group writeback /main/DUT/writeback/x_rd_write_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/dm_data_l_i add wave -noupdate -expand -group writeback /main/DUT/writeback/dm_data_l_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/dm_valid_l_i add wave -noupdate -expand -group writeback /main/DUT/writeback/dm_load_done_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/dm_store_done_i
add wave -noupdate -expand -group writeback /main/DUT/writeback/rf_rd_value_o add wave -noupdate -expand -group writeback /main/DUT/writeback/rf_rd_value_o
add wave -noupdate -expand -group writeback /main/DUT/writeback/rf_rd_o add wave -noupdate -expand -group writeback /main/DUT/writeback/rf_rd_o
add wave -noupdate -expand -group writeback /main/DUT/writeback/rf_rd_write_o add wave -noupdate -expand -group writeback /main/DUT/writeback/rf_rd_write_o
add wave -noupdate -expand -group writeback /main/DUT/writeback/load_value add wave -noupdate -expand -group writeback /main/DUT/writeback/load_value
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {14655000 ps} 0} WaveRestoreCursors {{Cursor 1} {13680175 ps} 0}
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
...@@ -178,4 +197,4 @@ configure wave -griddelta 40 ...@@ -178,4 +197,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ps configure wave -timelineunits ps
update update
WaveRestoreZoom {11530808 ps} {16159192 ps} WaveRestoreZoom {13606882 ps} {13751520 ps}
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