Skip to content

U
urv-core
Commit 6f77e1e8 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

core: fixed missing interrupts/exceptions bug

parent bc0aef8a
Hide whitespace changes
Inline Side-by-side
Showing with 38 additions and 28 deletions
rtl/urv_config.v
View file @ 6f77e1e8
...@@ -23,6 +23,6 @@ ...@@ -23,6 +23,6 @@
// SPARTAN6 - Xilinx Spartan-6 FPGA // SPARTAN6 - Xilinx Spartan-6 FPGA
// GENERIC - Generic, HW-independent // GENERIC - Generic, HW-independent
`define URV_PLATFORM_GENERIC 1 `define URV_PLATFORM_SPARTAN6 1
//`define URV_PLATFORM_ALTERA 1 //`define URV_PLATFORM_ALTERA 1
rtl/urv_exceptions.v
View file @ 6f77e1e8
...@@ -47,21 +47,21 @@ module urv_exceptions ...@@ -47,21 +47,21 @@ module urv_exceptions
input [31:0] x_csr_write_value_i, input [31:0] x_csr_write_value_i,
output x_exception_o, output reg x_exception_o,
input [31:0] x_exception_pc_i, input [31:0] x_exception_pc_i,
output [31:0] x_exception_pc_o, output [31:0] x_exception_pc_o,
output [31:0] x_exception_vector_o, output [31:0] x_exception_vector_o,
input x_exception_taken_i,
output [31:0] csr_mstatus_o, output [31:0] csr_mstatus_o,
output [31:0] csr_mip_o, output [31:0] csr_mip_o,
output [31:0] csr_mie_o, output [31:0] csr_mie_o,
output [31:0] csr_mepc_o, output [31:0] csr_mepc_o,
output [31:0] csr_mcause_o output [31:0] csr_mcause_o
); );
reg [31:0] csr_mepc; reg [31:0] csr_mepc;
reg [31:0] csr_mie; reg [31:0] csr_mie;
reg csr_ie; reg csr_ie;
...@@ -72,6 +72,7 @@ module urv_exceptions ...@@ -72,6 +72,7 @@ module urv_exceptions
reg [3:0] cause; reg [3:0] cause;
reg [5:0] except_vec_masked; reg [5:0] except_vec_masked;
reg exception_pending;
assign csr_mcause_o = {28'h0, csr_mcause}; assign csr_mcause_o = {28'h0, csr_mcause};
assign csr_mepc_o = csr_mepc; assign csr_mepc_o = csr_mepc;
...@@ -80,7 +81,7 @@ module urv_exceptions ...@@ -80,7 +81,7 @@ module urv_exceptions
assign csr_mstatus_o[31:1] = 0; assign csr_mstatus_o[31:1] = 0;
reg [31:0] csr_mip; reg [31:0] csr_mip;
always@* always@*
begin begin
csr_mip <= 0; csr_mip <= 0;
...@@ -91,12 +92,10 @@ module urv_exceptions ...@@ -91,12 +92,10 @@ module urv_exceptions
csr_mip[`EXCEPT_TIMER] <= except_vec_masked[4]; csr_mip[`EXCEPT_TIMER] <= except_vec_masked[4];
csr_mip[`EXCEPT_IRQ] <= except_vec_masked[5]; csr_mip[`EXCEPT_IRQ] <= except_vec_masked[5];
end end
assign csr_mip_o = csr_mip; assign csr_mip_o = csr_mip;
always@(posedge clk_i) always@(posedge clk_i)
if (rst_i) if (rst_i)
except_vec_masked <= 0; except_vec_masked <= 0;
...@@ -132,7 +131,6 @@ module urv_exceptions ...@@ -132,7 +131,6 @@ module urv_exceptions
always@* always@*
exception <= |except_vec_masked | exp_invalid_insn_i; exception <= |except_vec_masked | exp_invalid_insn_i;
reg exception_pending;
assign x_exception_vector_o = 'h8; assign x_exception_vector_o = 'h8;
...@@ -161,8 +159,7 @@ module urv_exceptions ...@@ -161,8 +159,7 @@ module urv_exceptions
end else if(!x_stall_i && !x_kill_i) begin end else if(!x_stall_i && !x_kill_i) begin
if ( d_is_eret_i ) if ( d_is_eret_i )
exception_pending <= 0; exception_pending <= 0;
else if ( x_exception_taken_i )
if ( !exception_pending && exception )
begin begin
csr_mepc <= x_exception_pc_i; csr_mepc <= x_exception_pc_i;
csr_mcause <= cause; csr_mcause <= cause;
...@@ -191,7 +188,14 @@ module urv_exceptions ...@@ -191,7 +188,14 @@ module urv_exceptions
assign x_exception_pc_o = csr_mepc; assign x_exception_pc_o = csr_mepc;
assign x_exception_o = exception & !exception_pending;
always@(posedge clk_i)
if (rst_i)
x_exception_o <= 0;
else if (x_exception_taken_i)
x_exception_o <= 0;
else if (exception && !exception_pending)
x_exception_o <= 1;
endmodule // urv_exceptions endmodule // urv_exceptions
......
rtl/urv_exec.v
View file @ 6f77e1e8
...@@ -117,7 +117,9 @@ module urv_exec ...@@ -117,7 +117,9 @@ module urv_exec
reg [31:0] alu_op1, alu_op2, alu_result; reg [31:0] alu_op1, alu_op2, alu_result;
reg [31:0] rd_value; reg [31:0] rd_value;
wire exception_taken;
reg branch_take; reg branch_take;
reg branch_condition_met; reg branch_condition_met;
...@@ -141,7 +143,9 @@ module urv_exec ...@@ -141,7 +143,9 @@ module urv_exec
wire [31:0] csr_mie, csr_mip, csr_mepc, csr_mstatus,csr_mcause; wire [31:0] csr_mie, csr_mip, csr_mepc, csr_mstatus,csr_mcause;
wire [31:0] csr_write_value; wire [31:0] csr_write_value;
wire [31:0] exception_address, exception_vector; wire [31:0] exception_address, exception_vector;
reg [31:0] exception_pc;
urv_csr csr_regs urv_csr csr_regs
( (
...@@ -194,18 +198,18 @@ module urv_exec ...@@ -194,18 +198,18 @@ module urv_exec
.exp_invalid_insn_i(d_is_undef_i && !x_stall_i && !x_kill_i && d_valid_i), .exp_invalid_insn_i(d_is_undef_i && !x_stall_i && !x_kill_i && d_valid_i),
.x_exception_o(exception), .x_exception_o(exception),
.x_exception_pc_i(d_pc_i), .x_exception_pc_i(exception_pc),
.x_exception_pc_o(exception_address), .x_exception_pc_o(exception_address),
.x_exception_vector_o(exception_vector), .x_exception_vector_o(exception_vector),
.x_exception_taken_i(exception_taken),
.csr_mstatus_o(csr_mstatus), .csr_mstatus_o(csr_mstatus),
.csr_mip_o(csr_mip), .csr_mip_o(csr_mip),
.csr_mie_o(csr_mie), .csr_mie_o(csr_mie),
.csr_mepc_o(csr_mepc), .csr_mepc_o(csr_mepc),
.csr_mcause_o(csr_mcause) .csr_mcause_o(csr_mcause)
); );
// branch condition decoding // branch condition decoding
always@* always@*
...@@ -416,8 +420,8 @@ module urv_exec ...@@ -416,8 +420,8 @@ module urv_exec
assign dm_load_o = d_is_load_i & d_valid_i & !x_kill_i & !x_stall_i & !exception; assign dm_load_o = d_is_load_i & d_valid_i & !x_kill_i & !x_stall_i & !exception;
assign dm_store_o = d_is_store_i & d_valid_i & !x_kill_i & !x_stall_i & !exception; assign dm_store_o = d_is_store_i & d_valid_i & !x_kill_i & !x_stall_i & !exception;
// X/W pipeline registers // X/W pipeline registers
always@(posedge clk_i) always@(posedge clk_i)
if (rst_i) begin if (rst_i) begin
...@@ -428,7 +432,7 @@ module urv_exec ...@@ -428,7 +432,7 @@ module urv_exec
end else if (!x_stall_i) begin end else if (!x_stall_i) begin
f_branch_target_o <= branch_target; f_branch_target_o <= branch_target;
f_branch_take <= branch_take && !x_kill_i && d_valid_i; f_branch_take <= branch_take && !x_kill_i && (d_valid_i || exception);
w_rd_o <= d_rd_i; w_rd_o <= d_rd_i;
w_rd_value_o <= rd_value; w_rd_value_o <= rd_value;
...@@ -442,9 +446,12 @@ module urv_exec ...@@ -442,9 +446,12 @@ module urv_exec
w_valid_o <= !exception; w_valid_o <= !exception;
end // else: !if(rst_i) end // else: !if(rst_i)
always@*
exception_pc <= d_pc_i;
assign f_branch_take_o = f_branch_take; assign f_branch_take_o = f_branch_take;
assign exception_taken = exception && (branch_take && !x_kill_i && (d_valid_i || exception));
// pipeline control: generate stall request signal // pipeline control: generate stall request signal
always@* always@*
// never stall on taken branch // never stall on taken branch
......
rtl/urv_iram.v
View file @ 6f77e1e8
...@@ -271,10 +271,10 @@ module urv_iram ...@@ -271,10 +271,10 @@ module urv_iram
$fscanf(f,"%s %08x %08x", cmd,addr,data); $fscanf(f,"%s %08x %08x", cmd,addr,data);
if(cmd == "write") if(cmd == "write")
begin begin
mem[addr % g_size][7:0] = data[31:24]; mem[addr % g_size][31:24] = data[31:24];
mem[addr % g_size][15:8] = data[23:16]; mem[addr % g_size][23:16] = data[23:16];
mem[addr % g_size][23:16] = data[15:8]; mem[addr % g_size][15:8] = data[15:8];
mem[addr % g_size][31:24] = data[7:0]; mem[addr % g_size][7:0] = data[7:0];
end end
end end
end // if (g_simulation && g_init_file != "") end // if (g_simulation && g_init_file != "")
...@@ -359,10 +359,9 @@ module urv_iram ...@@ -359,10 +359,9 @@ module urv_iram
assign qb_o = qb_int; assign qb_o = qb_int;
// synthesis translate_on
end // else: !if(!g_simulation) // end // else: !if(!g_simulation)
endmodule
`endif `endif
`ifdef URV_PLATFORM_ALTERA `ifdef URV_PLATFORM_ALTERA
......
rtl/xurv_core.vhd
View file @ 6f77e1e8
...@@ -237,7 +237,7 @@ begin ...@@ -237,7 +237,7 @@ begin
port map ( port map (
clk_i => clk_sys_i, clk_i => clk_sys_i,
rst_i => cpu_rst, rst_i => cpu_rst,
irq_i => '0', irq_i => irq_i(0),
im_addr_o => im_addr, im_addr_o => im_addr,
im_data_i => im_data, im_data_i => im_data,
im_valid_i => im_valid, im_valid_i => im_valid,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment