Commit 6f77e1e8 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

core: fixed missing interrupts/exceptions bug

parent bc0aef8a
......@@ -23,6 +23,6 @@
// SPARTAN6 - Xilinx Spartan-6 FPGA
// GENERIC - Generic, HW-independent
`define URV_PLATFORM_GENERIC 1
`define URV_PLATFORM_SPARTAN6 1
//`define URV_PLATFORM_ALTERA 1
......@@ -47,21 +47,21 @@ module urv_exceptions
input [31:0] x_csr_write_value_i,
output x_exception_o,
output reg x_exception_o,
input [31:0] x_exception_pc_i,
output [31:0] x_exception_pc_o,
output [31:0] x_exception_vector_o,
input x_exception_taken_i,
output [31:0] csr_mstatus_o,
output [31:0] csr_mip_o,
output [31:0] csr_mie_o,
output [31:0] csr_mepc_o,
output [31:0] csr_mcause_o
);
reg [31:0] csr_mepc;
reg [31:0] csr_mie;
reg csr_ie;
......@@ -72,6 +72,7 @@ module urv_exceptions
reg [3:0] cause;
reg [5:0] except_vec_masked;
reg exception_pending;
assign csr_mcause_o = {28'h0, csr_mcause};
assign csr_mepc_o = csr_mepc;
......@@ -80,7 +81,7 @@ module urv_exceptions
assign csr_mstatus_o[31:1] = 0;
reg [31:0] csr_mip;
always@*
begin
csr_mip <= 0;
......@@ -91,12 +92,10 @@ module urv_exceptions
csr_mip[`EXCEPT_TIMER] <= except_vec_masked[4];
csr_mip[`EXCEPT_IRQ] <= except_vec_masked[5];
end
assign csr_mip_o = csr_mip;
always@(posedge clk_i)
if (rst_i)
except_vec_masked <= 0;
......@@ -132,7 +131,6 @@ module urv_exceptions
always@*
exception <= |except_vec_masked | exp_invalid_insn_i;
reg exception_pending;
assign x_exception_vector_o = 'h8;
......@@ -161,8 +159,7 @@ module urv_exceptions
end else if(!x_stall_i && !x_kill_i) begin
if ( d_is_eret_i )
exception_pending <= 0;
if ( !exception_pending && exception )
else if ( x_exception_taken_i )
begin
csr_mepc <= x_exception_pc_i;
csr_mcause <= cause;
......@@ -191,7 +188,14 @@ module urv_exceptions
assign x_exception_pc_o = csr_mepc;
assign x_exception_o = exception & !exception_pending;
always@(posedge clk_i)
if (rst_i)
x_exception_o <= 0;
else if (x_exception_taken_i)
x_exception_o <= 0;
else if (exception && !exception_pending)
x_exception_o <= 1;
endmodule // urv_exceptions
......
......@@ -117,7 +117,9 @@ module urv_exec
reg [31:0] alu_op1, alu_op2, alu_result;
reg [31:0] rd_value;
wire exception_taken;
reg branch_take;
reg branch_condition_met;
......@@ -141,7 +143,9 @@ module urv_exec
wire [31:0] csr_mie, csr_mip, csr_mepc, csr_mstatus,csr_mcause;
wire [31:0] csr_write_value;
wire [31:0] exception_address, exception_vector;
reg [31:0] exception_pc;
urv_csr csr_regs
(
......@@ -194,18 +198,18 @@ module urv_exec
.exp_invalid_insn_i(d_is_undef_i && !x_stall_i && !x_kill_i && d_valid_i),
.x_exception_o(exception),
.x_exception_pc_i(d_pc_i),
.x_exception_pc_i(exception_pc),
.x_exception_pc_o(exception_address),
.x_exception_vector_o(exception_vector),
.x_exception_taken_i(exception_taken),
.csr_mstatus_o(csr_mstatus),
.csr_mip_o(csr_mip),
.csr_mie_o(csr_mie),
.csr_mepc_o(csr_mepc),
.csr_mcause_o(csr_mcause)
);
// branch condition decoding
always@*
......@@ -416,8 +420,8 @@ module urv_exec
assign dm_load_o = d_is_load_i & d_valid_i & !x_kill_i & !x_stall_i & !exception;
assign dm_store_o = d_is_store_i & d_valid_i & !x_kill_i & !x_stall_i & !exception;
// X/W pipeline registers
always@(posedge clk_i)
if (rst_i) begin
......@@ -428,7 +432,7 @@ module urv_exec
end else if (!x_stall_i) begin
f_branch_target_o <= branch_target;
f_branch_take <= branch_take && !x_kill_i && d_valid_i;
f_branch_take <= branch_take && !x_kill_i && (d_valid_i || exception);
w_rd_o <= d_rd_i;
w_rd_value_o <= rd_value;
......@@ -442,9 +446,12 @@ module urv_exec
w_valid_o <= !exception;
end // else: !if(rst_i)
always@*
exception_pc <= d_pc_i;
assign f_branch_take_o = f_branch_take;
assign exception_taken = exception && (branch_take && !x_kill_i && (d_valid_i || exception));
// pipeline control: generate stall request signal
always@*
// never stall on taken branch
......
......@@ -271,10 +271,10 @@ module urv_iram
$fscanf(f,"%s %08x %08x", cmd,addr,data);
if(cmd == "write")
begin
mem[addr % g_size][7:0] = data[31:24];
mem[addr % g_size][15:8] = data[23:16];
mem[addr % g_size][23:16] = data[15:8];
mem[addr % g_size][31:24] = data[7:0];
mem[addr % g_size][31:24] = data[31:24];
mem[addr % g_size][23:16] = data[23:16];
mem[addr % g_size][15:8] = data[15:8];
mem[addr % g_size][7:0] = data[7:0];
end
end
end // if (g_simulation && g_init_file != "")
......@@ -359,10 +359,9 @@ module urv_iram
assign qb_o = qb_int;
// synthesis translate_on
end // else: !if(!g_simulation)
// end // else: !if(!g_simulation)
endmodule
`endif
`ifdef URV_PLATFORM_ALTERA
......
......@@ -237,7 +237,7 @@ begin
port map (
clk_i => clk_sys_i,
rst_i => cpu_rst,
irq_i => '0',
irq_i => irq_i(0),
im_addr_o => im_addr,
im_data_i => im_data,
im_valid_i => im_valid,
......
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