Commit 695e8467 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wip

parent d36aadc8
...@@ -63,7 +63,7 @@ module rv_csr ...@@ -63,7 +63,7 @@ module rv_csr
always@* always@*
case(d_csr_sel_i) case(d_csr_sel_i) // synthesis full_case parallel_case
`CSR_ID_CYCLESL: csr_in1 <= csr_cycles_i[31:0]; `CSR_ID_CYCLESL: csr_in1 <= csr_cycles_i[31:0];
`CSR_ID_CYCLESH: csr_in1 <= { 24'h0, csr_cycles_i[39:32] }; `CSR_ID_CYCLESH: csr_in1 <= { 24'h0, csr_cycles_i[39:32] };
`CSR_ID_TIMEL: csr_in1 <= csr_time_i[31:0]; `CSR_ID_TIMEL: csr_in1 <= csr_time_i[31:0];
...@@ -100,7 +100,7 @@ module rv_csr ...@@ -100,7 +100,7 @@ module rv_csr
begin begin
always@* always@*
case(d_fun_i) case(d_fun_i) // synthesis full_case parallel_case
`CSR_OP_CSRRWI, `CSR_OP_CSRRWI,
`CSR_OP_CSRRW: `CSR_OP_CSRRW:
csr_out[i] <= csr_in2[i]; csr_out[i] <= csr_in2[i];
......
...@@ -2,6 +2,10 @@ ...@@ -2,6 +2,10 @@
`timescale 1ns/1ps `timescale 1ns/1ps
`define ARCH_VIRTEX6
`ifdef ARCH_SPARTAN6
module rv_mult18x18 module rv_mult18x18
( (
input clk_i, input clk_i,
...@@ -63,8 +67,31 @@ module rv_mult18x18 ...@@ -63,8 +67,31 @@ module rv_mult18x18
); );
endmodule // rv_mult18x18 endmodule // rv_mult18x18
`endif // `i
// fdef ARCH_SPARTAN6
`ifdef ARCH_VIRTEX6
module rv_mult18x18
(
input clk_i,
input rst_i,
input stall_i,
input [17:0] x_i,
input [17:0] y_i,
output reg [35:0] q_o
);
always@(posedge clk_i)
if(!stall_i)
q_o <= x_i * y_i;
endmodule // rv_mult18x18
`endif // `ifdef ARCH_VIRTEX6
module rv_multiply module rv_multiply
......
...@@ -318,18 +318,6 @@ module rv_decode ...@@ -318,18 +318,6 @@ module rv_decode
x_is_add_o <= 1; x_is_add_o <= 1;
endcase // case (d_opcode) endcase // case (d_opcode)
// x_is
// SUB instruction
// ~ ( d_opcode == OPC_OP &&
/*(d_opcode == `OPC_AUIPC) || (d_opcode == `OPC_JAL) ||
(d_opcode == `OPC_LUI) || (d_opcode == `OPC_JALR) ||
(!((d_opcode == `OPC_OP && d_fun == `FUNC_ADD && f_ir_i[30]) || (d_fun == `FUNC_SLT) || (d_fun == `FUNC_SLTU)));*/
// all multiply/divide instructions except MUL // all multiply/divide instructions except MUL
x_is_undef_o <= (d_opcode == `OPC_OP && f_ir_i[25] && d_fun != 3'b000); x_is_undef_o <= (d_opcode == `OPC_OP && f_ir_i[25] && d_fun != 3'b000);
......
# and don't touch the rest unless you know what you're doing. # and don't touch the rest unless you know what you're doing.
CROSS_COMPILE ?= /opt/gcc-riscv/bin/riscv64-unknown-elf- CROSS_COMPILE ?= /opt/gcc-riscv-5.2.0/bin/riscv64-unknown-elf-
CC = $(CROSS_COMPILE)gcc CC = $(CROSS_COMPILE)gcc
LD = $(CROSS_COMPILE)ld LD = $(CROSS_COMPILE)ld
...@@ -7,13 +7,19 @@ OBJDUMP = $(CROSS_COMPILE)objdump ...@@ -7,13 +7,19 @@ OBJDUMP = $(CROSS_COMPILE)objdump
OBJCOPY = $(CROSS_COMPILE)objcopy OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size SIZE = $(CROSS_COMPILE)size
CFLAGS = -g -O2 -m32 -msoft-float -march=RV32I -I. -I../common -DSIM ARCH = RV32IM
OBJS = ../common/crtuser.o main.o ../common/uart.o ../common/printf.o ../common/vsprintf-xint.o
LDS = ../common/ram2.ld CFLAGS = -g -m32 -O2 -msoft-float -march=$(ARCH) -I. -I../common -ffunction-sections -fdata-sections -DFLAGS_STR="\"\"" -I../coremark_v1.0/barebones -I../coremark_v1.0
OBJS = ../common/crtuser.o main.o ../common/uart.o ../common/printf.o ../common/vsprintf-xint.o \
../coremark_v1.0/core_list_join.o ../coremark_v1.0/core_matrix.o ../coremark_v1.0/core_state.o ../coremark_v1.0/barebones/cvt.o \
../coremark_v1.0/core_main.o ../coremark_v1.0/barebones/core_portme.o ../coremark_v1.0/core_util.o ../coremark_v1.0/barebones/ee_printf.o ../coremark_v1.0/fmod.o
LDS = ../common/user.ld
OUTPUT=hello OUTPUT=hello
$(OUTPUT): $(LDS) $(OBJS) $(OUTPUT): $(LDS) $(OBJS)
${CC} -g -m32 -msoft-float -march=RV32I -o $(OUTPUT).elf -nostartfiles $(OBJS) -lm -L../coremark_v1.0 -lcoremark -T $(LDS) ${CC} -m32 -flto -Wl,--gc-sections -g -msoft-float -march=$(ARCH) -o $(OUTPUT).elf -nostartfiles $(OBJS) -lm -T $(LDS) -lc
${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin ${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -D $(OUTPUT).elf > disasm.S ${OBJDUMP} -D $(OUTPUT).elf > disasm.S
../genraminit $(OUTPUT).bin 16384 > $(OUTPUT).ram ../genraminit $(OUTPUT).bin 16384 > $(OUTPUT).ram
...@@ -24,4 +30,4 @@ clean: ...@@ -24,4 +30,4 @@ clean:
rm -f $(OUTPUT).elf $(OUTPUT).bin $(OBJS) rm -f $(OUTPUT).elf $(OUTPUT).bin $(OBJS)
%.o: %.S %.o: %.S
${CC} -c -m32 $^ -o $@ ${CC} -c -m32 -march=RV32IM $^ -o $@
\ No newline at end of file \ No newline at end of file
...@@ -55,15 +55,16 @@ main() ...@@ -55,15 +55,16 @@ main()
int i; int i;
for(i=0;i<100;i++) /* for(i=0;i<100;i++)
{ {
float f = 2*3.14*(float)i / 100.0; float f = 2*3.14*(float)i / 100.0;
int y = (int) (1000.0 *sin(f)); int y = (int) (1000.0 *sin(f));
pp_printf("%d %d\n", i, y); pp_printf("%d %d\n", i, y);
} }*/
// coremark_main(argc, argv); pp_printf("Starting CoreMark 1.0\n");
coremark_main(argc, argv);
for(;;); for(;;);
......
...@@ -7,9 +7,9 @@ OBJDUMP = $(CROSS_COMPILE)objdump ...@@ -7,9 +7,9 @@ OBJDUMP = $(CROSS_COMPILE)objdump
OBJCOPY = $(CROSS_COMPILE)objcopy OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size SIZE = $(CROSS_COMPILE)size
CFLAGS = -m32 CFLAGS = -m32 -DSIM -I../common -march=RV32I -O2
OBJS = test.S OBJS = test.o ../common/crt0.o ../common/irq.o ../common/emulate.o ../common/uart.o ../common/printf.o ../common/vsprintf-xint.o
LDS = ../ram.ld LDS = ../common/ram2.ld
OUTPUT=test1 OUTPUT=test1
$(OUTPUT): $(LDS) $(OBJS) $(OUTPUT): $(LDS) $(OBJS)
......
.section .boot, "ax", @progbits .text
.global _start .global main2
_start: main2:
li t0, 1000
li t1, 7
div t2,t0,t1
li t0,2000
divu t2,t0,t1
la a5, lab1 forever:
lw a5, 0(a5) j forever
jr a5 \ No newline at end of file
forever:
j forever
lab1:
.word continue
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
continue:
nop
j continue
/* sw x5,-16(x1)
nop
nop
lw x31, -16(x1)
la x30, 0x1235
beq x30, x31, pass1
fail1:
nop
j fail1
pass1:
lw x20,-8(x1) // x20 = 0xffec
lw x20,0(x20) // x20 = 0x1235
addi x20,x20,1
sw x20,-20(x1)
*/
/*
slli t0, t0, 0x1
sw t0,-4(sp)
slli t0, t0, 0x1
sw t0,-8(sp)
la t0, 0xffffffa0
srli t0, t0, 0x1
sw t0,-4(sp)
srli t0, t0, 0x1
sw t0,-8(sp)
*/
...@@ -8,7 +8,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy ...@@ -8,7 +8,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size SIZE = $(CROSS_COMPILE)size
CFLAGS = -g -m32 -msoft-float -march=RV32I -O2 CFLAGS = -g -m32 -msoft-float -march=RV32I -O2
OBJS = ../common/crt0.o ../common/irq.o main.o OBJS = ../common/crt0.o ../common/irq.o main.o ../common/uart.o ../common/vsprintf-xint.o ../common/printf.o
LDS = ../common/ram2.ld LDS = ../common/ram2.ld
OUTPUT=test2 OUTPUT=test2
......
...@@ -177,7 +177,7 @@ uint32_t sys_get_cycles() ...@@ -177,7 +177,7 @@ uint32_t sys_get_cycles()
volatile int irq_counter = 0; volatile int irq_counter = 0;
void handle_trap() void irq_handler()
{ {
irq_counter++; irq_counter++;
} }
......
../benchmarks/dhrystone/dhrystone.ram
rv32ui-p-csr.ram rv32ui-p-csr.ram
rv32ui-p-addi.ram rv32ui-p-addi.ram
rv32ui-p-add.ram rv32ui-p-add.ram
......
...@@ -49,7 +49,7 @@ ...@@ -49,7 +49,7 @@
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
...@@ -128,7 +128,7 @@ ...@@ -128,7 +128,7 @@
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
...@@ -150,7 +150,7 @@ ...@@ -150,7 +150,7 @@
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/> <property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Map" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
...@@ -179,8 +179,8 @@ ...@@ -179,8 +179,8 @@
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/> <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
......
...@@ -133,7 +133,7 @@ begin -- rtl ...@@ -133,7 +133,7 @@ begin -- rtl
DIVCLK_DIVIDE => 1, DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8, CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000, CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10, -- 62.5 MHz CLKOUT0_DIVIDE => 7, -- 62.5 MHz
CLKOUT0_PHASE => 0.000, CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- not used CLKOUT1_DIVIDE => 8, -- not used
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment