Commit 51d4addc authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

optimizing bypass...

parent de6bfd7b
......@@ -257,8 +257,7 @@ module rv_cpu
.clk_i(clk_i),
.rst_i(rst_i),
.x_stall_i(x_stall),
.w_stall_i(w_stall),
.d_stall_i(d_stall),
.rf_rs1_i(rf_rs1),
.rf_rs2_i(rf_rs2),
......
......@@ -24,12 +24,10 @@
module rv_regmem
(
input clk_i,
input rst_i,
input en1_i,
input en2_i,
input [4:0] a1_i,
output [31:0] q1_o,
......@@ -48,6 +46,7 @@ module rv_regmem
reg [31:0] q1_int;
always@(posedge clk_i)
if(en1_i)
q1_int <= ram[a1_i];
always@(posedge clk_i)
......@@ -96,8 +95,7 @@ module rv_regfile
input clk_i,
input rst_i,
input x_stall_i,
input w_stall_i,
input d_stall_i,
input [4:0] rf_rs1_i,
input [4:0] rf_rs2_i,
......@@ -125,6 +123,7 @@ module rv_regfile
rv_regmem bank0 (
.clk_i(clk_i),
.rst_i (rst_i ),
.en1_i(!d_stall_i),
.a1_i(rf_rs1_i),
.q1_o(rs1_regfile),
......@@ -136,7 +135,7 @@ module rv_regfile
rv_regmem bank1 (
.clk_i(clk_i),
.rst_i (rst_i ),
.en1_i(!d_stall_i),
.a1_i(rf_rs2_i),
.q1_o(rs2_regfile),
......
......@@ -129,7 +129,8 @@ begin
end if;
end process;
dm_is_wishbone <= '1' when unsigned(dm_addr(g_address_bits-1 downto 0)) >= g_wishbone_start else '0';
-- dm_is_wishbone <= '1' when unsigned(dm_addr(20g_address_bits-1 downto 0)) >= g_wishbone_start else '0';
dm_is_wishbone <= dm_addr(31);
-- Wishbone bus arbitration / internal RAM access
process(clk_sys_i)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment