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urv-core
Commit 1cc11f80 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fixed dropped jump if followed by multicycle instruction

parent a9fae1ac
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Showing with 134 additions and 112 deletions
main.sv
View file @ 1cc11f80
...@@ -217,6 +217,36 @@ module main; ...@@ -217,6 +217,36 @@ module main;
endfunction // decode_regname endfunction // decode_regname
task automatic verify_branch(input [31:0] rs1, input[31:0] rs2, input take, input [2:0] fun);
int do_take;
case(fun)
`BRA_EQ: do_take = (rs1 == rs2);
`BRA_NEQ: do_take = (rs1 != rs2);
`BRA_GE: do_take = $signed(rs1) >= $signed(rs2);
`BRA_LT: do_take = $signed(rs1) < $signed(rs2);
`BRA_GEU: do_take = rs1 >= rs2;
`BRA_LTU: do_take = rs1 < rs2;
default:
begin
$error("illegal branch func");
$stop;
end
endcase // case (func)
if(do_take != take)
begin
$error("fucked up jump");
$stop;
end
endtask // verify_branch
function automatic string s_hex(int x); function automatic string s_hex(int x);
return $sformatf("%s0x%-08x", x<0?"-":" ", (x<0)?(-x):x); return $sformatf("%s0x%-08x", x<0?"-":" ", (x<0)?(-x):x);
endfunction // s_hex endfunction // s_hex
...@@ -345,7 +375,11 @@ module main; ...@@ -345,7 +375,11 @@ module main;
opc = "branch"; opc = "branch";
fun = decode_cond(DUT.d2x_fun); fun = decode_cond(DUT.d2x_fun);
//decode_op(DUT.d2x_fun); //decode_op(DUT.d2x_fun);
args = $sformatf("%-3s %-3s 0x%-08x %s", rs1, rs2, DUT.execute.branch_target, DUT.execute.branch_take?"TAKE":"IGNORE"); args = $sformatf("%-3s %-3s 0x%-08x rs1 %s", rs1, rs2, DUT.execute.branch_target, DUT.execute.branch_take?"TAKE":"IGNORE");
verify_branch(DUT.execute.rs1, DUT.execute.rs2, DUT.execute.branch_take,DUT.d2x_fun);
end end
`OPC_LOAD: `OPC_LOAD:
begin begin
...@@ -366,6 +400,7 @@ module main; ...@@ -366,6 +400,7 @@ module main;
$display("%08x: %-8s %-3s %s", DUT.execute.d_pc_i, opc, fun, args); $display("%08x: %-8s %-3s %s", DUT.execute.d_pc_i, opc, fun, args);
$fwrite(f_exec_log,"%08x: %-8s %-3s %s\n", DUT.execute.d_pc_i, opc, fun, args); $fwrite(f_exec_log,"%08x: %-8s %-3s %s\n", DUT.execute.d_pc_i, opc, fun, args);
$fwrite(f_exec_log,": PC %08x OP %08x\n", DUT.execute.d_pc_i, DUT.decode.x_ir);
......
rv_exec.v
View file @ 1cc11f80
...@@ -55,7 +55,7 @@ input w_stall_req_i, ...@@ -55,7 +55,7 @@ input w_stall_req_i,
input d_is_shift_i, input d_is_shift_i,
output reg [31:0] f_branch_target_o, output reg [31:0] f_branch_target_o,
output reg f_branch_take_o, output f_branch_take_o,
output w_load_hazard_o, output w_load_hazard_o,
...@@ -104,6 +104,9 @@ input w_stall_req_i, ...@@ -104,6 +104,9 @@ input w_stall_req_i,
wire cmp_equal = (cmp_op1 == cmp_op2); wire cmp_equal = (cmp_op1 == cmp_op2);
wire cmp_lt = cmp_rs[32]; wire cmp_lt = cmp_rs[32];
reg f_branch_take;
// branch condition decoding // branch condition decoding
always@* always@*
case (d_fun_i) case (d_fun_i)
...@@ -203,9 +206,11 @@ input w_stall_req_i, ...@@ -203,9 +206,11 @@ input w_stall_req_i,
); );
always@(posedge clk_i) always@(posedge clk_i)
shifter_req_d0 <= shifter_req; if(shifter_req_d0 && !x_stall_i)
shifter_req_d0 <= 0;
else
shifter_req_d0 <= shifter_req;
wire shifter_stall_req = shifter_req && !shifter_req_d0; wire shifter_stall_req = shifter_req && !shifter_req_d0;
...@@ -230,7 +235,8 @@ input w_stall_req_i, ...@@ -230,7 +235,8 @@ input w_stall_req_i,
// generate load/store address // generate load/store address
always@* always@*
begin begin
dm_addr <= rs1 + $signed(d_imm_i[11:0]); dm_addr <= rs1 + d_imm_i;
//[11:0]);
end end
...@@ -299,7 +305,7 @@ input w_stall_req_i, ...@@ -299,7 +305,7 @@ input w_stall_req_i,
always@(posedge clk_i) always@(posedge clk_i)
if (rst_i) begin if (rst_i) begin
f_branch_target_o <= 0; f_branch_target_o <= 0;
f_branch_take_o <= 0; f_branch_take <= 0;
w_rd_write_o <= 0; w_rd_write_o <= 0;
w_rd_o <= 0; w_rd_o <= 0;
w_fun_o <= 0; w_fun_o <= 0;
...@@ -310,7 +316,7 @@ input w_stall_req_i, ...@@ -310,7 +316,7 @@ input w_stall_req_i,
end else if (!x_stall_i) begin end else if (!x_stall_i) begin
f_branch_target_o <= branch_target; f_branch_target_o <= branch_target;
f_branch_take_o <= branch_take && !x_kill_i && d_valid_i; f_branch_take <= branch_take && !x_kill_i && d_valid_i;
w_rd_o <= d_rd_i; w_rd_o <= d_rd_i;
...@@ -326,16 +332,18 @@ input w_stall_req_i, ...@@ -326,16 +332,18 @@ input w_stall_req_i,
w_dm_addr_o <= dm_addr; w_dm_addr_o <= dm_addr;
end else begin // if (!x_stall_i) end else begin // if (!x_stall_i)
f_branch_take_o <= 0; f_branch_take <= 0;
w_rd_write_o <= 0; w_rd_write_o <= 0;
w_load_o <= 0; w_load_o <= 0;
w_store_o <= 0; w_store_o <= 0;
end // else: !if(rst_i) end // else: !if(rst_i)
assign f_branch_take_o = f_branch_take;
assign x_stall_req_o = shifter_stall_req || ((is_store || is_load) && !dm_ready_i); assign x_stall_req_o = !f_branch_take && (shifter_stall_req || ((is_store || is_load) && !dm_ready_i));
assign w_load_hazard_o = d_load_hazard_i; assign w_load_hazard_o = d_load_hazard_i;
......
rv_predecode.v
View file @ 1cc11f80
...@@ -85,6 +85,8 @@ module rv_decode ...@@ -85,6 +85,8 @@ module rv_decode
rf_rs1_o <= f_rs1; rf_rs1_o <= f_rs1;
rf_rs2_o <= f_rs2; rf_rs2_o <= f_rs2;
end end
reg[31:0] x_ir;
always@(posedge clk_i) always@(posedge clk_i)
if(rst_i) if(rst_i)
...@@ -94,6 +96,8 @@ module rv_decode ...@@ -94,6 +96,8 @@ module rv_decode
end else if(!d_stall_i) begin end else if(!d_stall_i) begin
x_valid_o <= f_valid_i && !d_kill_i; x_valid_o <= f_valid_i && !d_kill_i;
x_pc_o <= f_pc_i; x_pc_o <= f_pc_i;
x_ir <= f_ir_i;
end end
wire [4:0] d_opcode = f_ir_i[6:2]; wire [4:0] d_opcode = f_ir_i[6:2];
......
wave.do
View file @ 1cc11f80
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