Commit 14e06a77 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

fixed wait states on long reads/writes

parent b2bc141b
...@@ -285,8 +285,8 @@ module rv_exec ...@@ -285,8 +285,8 @@ module rv_exec
wire is_load = (d_opcode_i == `OPC_LOAD ? 1: 0) && d_valid_i && !x_kill_i; wire is_load = (d_opcode_i == `OPC_LOAD ? 1: 0) && d_valid_i && !x_kill_i;
wire is_store = (d_opcode_i == `OPC_STORE ? 1: 0) && d_valid_i && !x_kill_i; wire is_store = (d_opcode_i == `OPC_STORE ? 1: 0) && d_valid_i && !x_kill_i;
assign dm_load_o = is_load && !x_stall_i; assign dm_load_o = is_load;
assign dm_store_o = is_store && !x_stall_i; assign dm_store_o = is_store;
always@(posedge clk_i) always@(posedge clk_i)
if (rst_i) begin if (rst_i) begin
...@@ -318,7 +318,7 @@ module rv_exec ...@@ -318,7 +318,7 @@ module rv_exec
w_dm_addr_o <= dm_addr; w_dm_addr_o <= dm_addr;
end else begin // if (!x_stall_i) end else begin // if (!x_stall_i)
f_branch_take <= 0; // f_branch_take <= 0;
w_rd_write_o <= 0; w_rd_write_o <= 0;
w_load_o <= 0; w_load_o <= 0;
w_store_o <= 0; w_store_o <= 0;
......
...@@ -97,10 +97,28 @@ module rv_writeback ...@@ -97,10 +97,28 @@ module rv_writeback
end // always@ * end // always@ *
reg pending_load = 0, pending_store = 0, pending_load_hazard = 0;
always@(posedge clk_i)
begin
if(x_load_i && !dm_load_done_i) begin
pending_load <= 1;
pending_load_hazard <= x_load_hazard_i;
end else if (dm_load_done_i) begin
pending_load <= 0;
pending_load_hazard <= 0;
end
if(x_store_i && !dm_store_done_i)
pending_store <= 1;
else if (dm_store_done_i)
pending_store <= 0;
end
reg interlock_d = 0; reg interlock_d = 0;
wire interlock = (x_load_i && dm_load_done_i && x_load_hazard_i); wire interlock = ( ( x_load_i || pending_load ) && dm_load_done_i && (x_load_hazard_i || pending_load_hazard ) );
always@(posedge clk_i) always@(posedge clk_i)
begin begin
...@@ -113,9 +131,9 @@ module rv_writeback ...@@ -113,9 +131,9 @@ module rv_writeback
assign rf_rd_value_o = (x_load_i ? load_value : x_rd_value_i ); assign rf_rd_value_o = (x_load_i ? load_value : x_rd_value_i );
assign rf_rd_o = (x_rd_i); assign rf_rd_o = (x_rd_i);
assign rf_rd_write_o = !interlock_d && (w_stall_i ? 1'b0 : (x_load_i && dm_load_done_i ? 1'b1 : x_rd_write_i )); assign rf_rd_write_o = !interlock_d && (w_stall_i ? 1'b0 : ((x_load_i || pending_load) && dm_load_done_i ? 1'b1 : x_rd_write_i ));
assign w_stall_req_o = (x_load_i && !dm_load_done_i) || (x_store_i && !dm_store_done_i) || (interlock && !interlock_d); assign w_stall_req_o = (pending_load && !dm_load_done_i) || (pending_store && !dm_store_done_i) || (interlock && !interlock_d);
......
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