Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
U
urv-core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
3
Issues
3
List
Board
Labels
Milestones
Merge Requests
2
Merge Requests
2
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
urv-core
Commits
14e06a77
Commit
14e06a77
authored
May 27, 2015
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fixed wait states on long reads/writes
parent
b2bc141b
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
24 additions
and
6 deletions
+24
-6
rv_exec.v
rv_exec.v
+3
-3
rv_writeback.v
rv_writeback.v
+21
-3
No files found.
rv_exec.v
View file @
14e06a77
...
...
@@ -285,8 +285,8 @@ module rv_exec
wire
is_load
=
(
d_opcode_i
==
`OPC_LOAD
?
1
:
0
)
&&
d_valid_i
&&
!
x_kill_i
;
wire
is_store
=
(
d_opcode_i
==
`OPC_STORE
?
1
:
0
)
&&
d_valid_i
&&
!
x_kill_i
;
assign
dm_load_o
=
is_load
&&
!
x_stall_i
;
assign
dm_store_o
=
is_store
&&
!
x_stall_i
;
assign
dm_load_o
=
is_load
;
assign
dm_store_o
=
is_store
;
always
@
(
posedge
clk_i
)
if
(
rst_i
)
begin
...
...
@@ -318,7 +318,7 @@ module rv_exec
w_dm_addr_o
<=
dm_addr
;
end
else
begin
// if (!x_stall_i)
f_branch_take
<=
0
;
//
f_branch_take <= 0;
w_rd_write_o
<=
0
;
w_load_o
<=
0
;
w_store_o
<=
0
;
...
...
rv_writeback.v
View file @
14e06a77
...
...
@@ -97,10 +97,28 @@ module rv_writeback
end
// always@ *
reg
pending_load
=
0
,
pending_store
=
0
,
pending_load_hazard
=
0
;
always
@
(
posedge
clk_i
)
begin
if
(
x_load_i
&&
!
dm_load_done_i
)
begin
pending_load
<=
1
;
pending_load_hazard
<=
x_load_hazard_i
;
end
else
if
(
dm_load_done_i
)
begin
pending_load
<=
0
;
pending_load_hazard
<=
0
;
end
if
(
x_store_i
&&
!
dm_store_done_i
)
pending_store
<=
1
;
else
if
(
dm_store_done_i
)
pending_store
<=
0
;
end
reg
interlock_d
=
0
;
wire
interlock
=
(
x_load_i
&&
dm_load_done_i
&&
x_load_hazard_i
)
;
wire
interlock
=
(
(
x_load_i
||
pending_load
)
&&
dm_load_done_i
&&
(
x_load_hazard_i
||
pending_load_hazard
)
)
;
always
@
(
posedge
clk_i
)
begin
...
...
@@ -113,9 +131,9 @@ module rv_writeback
assign
rf_rd_value_o
=
(
x_load_i
?
load_value
:
x_rd_value_i
)
;
assign
rf_rd_o
=
(
x_rd_i
)
;
assign
rf_rd_write_o
=
!
interlock_d
&&
(
w_stall_i
?
1'b0
:
(
x_load_i
&&
dm_load_done_i
?
1'b1
:
x_rd_write_i
))
;
assign
rf_rd_write_o
=
!
interlock_d
&&
(
w_stall_i
?
1'b0
:
(
(
x_load_i
||
pending_load
)
&&
dm_load_done_i
?
1'b1
:
x_rd_write_i
))
;
assign
w_stall_req_o
=
(
x_load_i
&&
!
dm_load_done_i
)
||
(
x_store_i
&&
!
dm_store_done_i
)
||
(
interlock
&&
!
interlock_d
)
;
assign
w_stall_req_o
=
(
pending_load
&&
!
dm_load_done_i
)
||
(
pending_store
&&
!
dm_store_done_i
)
||
(
interlock
&&
!
interlock_d
)
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment