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urv-core
Commits
01d9672d
Commit
01d9672d
authored
Sep 15, 2022
by
Tristan Gingold
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Add more urv specific tests (ecc), add urv_asm.h
parent
5d903309
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6 changed files
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148 additions
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14 deletions
+148
-14
tests-urv.lst
sw/testsuite/isa/tests-urv.lst
+3
-0
Makefrag
sw/testsuite/isa/urv/Makefrag
+3
-1
fix_ecc_1.S
sw/testsuite/isa/urv/fix_ecc_1.S
+62
-0
fix_ecc_2.S
sw/testsuite/isa/urv/fix_ecc_2.S
+62
-0
urv_asm.h
sw/testsuite/isa/urv/urv_asm.h
+7
-0
write_ecc.S
sw/testsuite/isa/urv/write_ecc.S
+11
-13
No files found.
sw/testsuite/isa/tests-urv.lst
0 → 100644
View file @
01d9672d
urv-p-write_ecc.ram
urv-p-fix_ecc_1.ram
urv-p-fix_ecc_2.ram
sw/testsuite/isa/urv/Makefrag
View file @
01d9672d
...
...
@@ -3,7 +3,9 @@
#-----------------------------------------------------------------------
urv_ecc_tests = \
write_ecc
write_ecc \
fix_ecc_1 \
fix_ecc_2
urv_p_tests = $(addprefix urv-p-, $(urv_ecc_tests))
...
...
sw/testsuite/isa/urv/fix_ecc_1.S
0 → 100644
View file @
01d9672d
# See LICENSE for license details.
#*****************************************************************************
# write_ecc.S
#-----------------------------------------------------------------------------
#
# Test write_ecc trap.
#
#include "riscv_test.h"
#include "test_macros.h"
#include "urv_asm.h"
RVTEST_RV32S
RVTEST_CODE_BEGIN
li TESTNUM, 2
li t2, 2
li t1, 1
# Write bad ECC for t2
write_ecc t2,t2,t1
nop # avoid bypass
nop
nop
# Use t2
addi t2,t2,1
j fail # Skipped by handler
# Check t2 has not been modified
addi t2,t2,1
j fail # Skipped by handler
# Fix t2
fix_ecc t2,t2,t2
j 1f # Handler not executed, so this is executed
j fail
1: addi t2,t2,1
j 1f
j fail
1: j pass
TEST_PASSFAIL
.globl trap_entry
trap_entry:
# Destroy t1, t0
li t1, CAUSE_ECC_ERROR
csrr t0, mcause
bne t0, t1, fail
# Inc address by 8
csrr t0, mepc
addi t0, t0, 8
csrw mepc, t0
mret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
sw/testsuite/isa/urv/fix_ecc_2.S
0 → 100644
View file @
01d9672d
# See LICENSE for license details.
#*****************************************************************************
# write_ecc.S
#-----------------------------------------------------------------------------
#
# Test write_ecc trap.
#
#include "riscv_test.h"
#include "test_macros.h"
#include "urv_asm.h"
RVTEST_RV32S
RVTEST_CODE_BEGIN
li TESTNUM, 2
li t2, 2
li t1, 2
# Write bad ECC for t2
write_ecc t2,t2,t1
nop # avoid bypass
nop
nop
# Use t2
add t3,t1,t2
j fail # Skipped by handler
# Check t2 has not been modified
add t3,t1,t2
j fail # Skipped by handler
# Fix t2
fix_ecc t2,t2,t2
j 1f # Handler not executed, so this is executed
j fail
1: add t3,t2,t2
j 1f
j fail
1: j pass
TEST_PASSFAIL
.globl trap_entry
trap_entry:
# Destroy t1, t0
li t1, CAUSE_ECC_ERROR
csrr t0, mcause
bne t0, t1, fail
# Inc address by 8
csrr t0, mepc
addi t0, t0, 8
csrw mepc, t0
mret
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
sw/testsuite/isa/urv/urv_asm.h
0 → 100644
View file @
01d9672d
.
macro
write_ecc
rd
rs1
rs2
.
insn
r
0x5b
,
0x1
,
0
,
\
rd
,
\
rs1
,
\
rs2
.
endm
.
macro
fix_ecc
rd
rs1
rs2
.
insn
r
0x5b
,
0x5
,
0
,
\
rd
,
\
rs1
,
\
rs2
.
endm
sw/testsuite/isa/urv/write_ecc.S
View file @
01d9672d
...
...
@@ -9,45 +9,43 @@
#include "riscv_test.h"
#include "test_macros.h"
#define write_ecc(rd,rs1,rs2) \
.long 0x5b | (rd << 7) | (rs1 << 15) | (rs2 << 20) | (1 << 12)
#include "urv_asm.h"
RVTEST_RV32S
RVTEST_CODE_BEGIN
li TESTNUM, 2
li t2, 0
#t2 is reg 7
li t2, 0
# No bad ECC
write_ecc
(7,7,7)
write_ecc
t2,t2,t2
nop # avoid bypass
nop
nop
# Use
reg 7
# Use
t2
addi t2,t2,1
j 1f # Not skipped
j fail
1: li t2, 2
li t1, 1 #t1 is reg 6
# Write bad ECC for
reg 7
write_ecc
(7,7,6)
# Write bad ECC for
t2
write_ecc
t2,t2,t1
nop # avoid bypass
nop
nop
# Use
reg 7
# Use
t2
addi t2,t2,1
j fail # Skipped by handler
li t1, 2
li t2, 3
# Write bad ECC for
reg 7
write_ecc
(7,7,6)
# Write bad ECC for
t2
write_ecc
t2,t2,t1
nop # avoid bypass
nop
nop
# Use
reg 7
add t3,t
2
,t2
# Use
t2
add t3,t
1
,t2
j fail # Skipped by handler
j pass
...
...
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