A: No, you cannot use any FMC card. The FMC standard allows many options
in the use of the signals on the FMC connector. Signalling levels,
differential or single ended signals and the level of Vadj may all be
chosen rather freely. And of course there is the major option of using a
High Pin-Count (HPC) or Low Pin-Count (LPC) connector which has, indeed,
less pins than the HPC.
To make the SVEC design simple, we had to make some design choices that
may make it not be compatible the FMC mezzanines you'd like to use.
The card uses an LPC connector.
Vadj is fixed to 2.5 Volt, i.e. the signalling levels are 2.5V
FMC connectivity: all 34 differential pairs connected, 1 GTP
transceiver with clock, 2 clock pairs, JTAG.
To fully check for compatibility the best thing is to verify, signal by
signal, the connections in the schematic of the SVEC and of the
mezzanine you want to use. You may let
us know once you've done this
excercise for a particular mezzanine and we possibly can add it to a
list of compatible
Q: Does the SVEC work in a 'classic' VME crate as opposed to a VME64x crate?
A: No, the SVEC does not work in a classic VME crate. Notably the 3V3
supply is taken from the D-row of the connector. The D and Z rows are
the additional rows that are added on the VME64x connector. These two
rows do not exist in the classic VME specification. Actually a classic
VME crate does not have a 3V3 supply at all.
Q: Is the FPGA programmable from the JTAG header on the board?
A: Yes, both FPGAs are programmable from the JTAG header on the board.
After powering down you will loose the configuration.
With this same JTAG header you can also program the Configuration EEPROM
that is connected to the "system FPGA", so that the "system FPGA" can
start up with the firmware that is preloaded into the EEPROM.
The "system FPGA" firmware allows access to the EEPROM from the VME and
also to load the "application FPGA" with a firmware located in the
EEPROM. See the
svec-gateware-manual for details.
Actually the board will be delivered with the "system FPGA" EEPROM
pre-loaded with a VME bus interface (the bootloader). With a program
writing over the VME bus one is able to program the "application FPGA"
who would then take over the control of the VME bus and disable the
A: The IMPACT flasher needs an Intel HEX-formatted file as .mcs. You can
prepare the MCS file from the binary flash image by using "Create PROM
File" flow in Impact and clicking through all the wizards (the flash
type is M25P128) or by using Xilinx's promgen tool directly:
where image.bin is the binary file made by following the steps from
section 4.3.1 of the Gateware Manual.
Q: Is there a FPGA reference design available?
A: We have not yet a fully documented reference design. However, the
"Golden bitstream" is a good start. This is the code that will be loaded
in the "application FPGA" and that is able to read the I2C bus on the
mezzanines. For the "system FPGA" you may look at the bootloader
Q: What version of the Xilinx tools are you using?
A: We use Xilinx ISE. Currently versions 13.3 and 14.1 are working fine.
Q: The VME flasher utility says "the bootloader is too old".
A: It's probably right... The first version of the bootloader that was
shipped with early series of the SVEC cards did not support booting the
AFPGA from Flash and re-programming it through VME. This feature has
been added in the second version of the bootloader. The instructions for
updating are in the
Q: In my system the extended pins (rows z and d) on connectors P1/P2 will be left unconnected. What to do?
A: Just don’t put these lines in the .ucf file and then the Xilinx tool
will find a safe solution for these pins.
Q: Is it possible to simulate the project with Xilinx ISIM?
A: To that advantage of the SystemVerilog VME bus functional model, you
need a simulator with SV support. Nevertheless, a VME testbench in vhdl
is available (see hdl/sim/ddr_test/).
Q: Are all necessary files uploaded on the GIT repository?
A: The SVEC GIT repository relies on sub-modules. Therefore, you have to
run the following commands (from the toplevel):
git submodule initgit submodule update
Erik van der Bij, Tom Wlostowski, Matthieu Cattin - 30 September 2014