Backplane buffers for ports 12-15 and 17-20 are enabled during FPGA boot
Because FPGA [1] has internal pin pull-ups (~25k) enabled during FPGA boot this might cause issues for back plane ports 12-15 and 17-20 during FPGA boot.
- PORTs 12-15: buffers [2] (BXT1, BXT2) have active HI output enable
and this pins have internal 20k resistor. This would mean that output
enable pin would have ~1.1V on its input which is between max LO (0.8V)
and min HI level (2V) therefore output state would not be defined.
FIX: adding external 5k (or smaller) pull-down on output enable pins.
- PORTs 17-20 : buffers [3] (MTB1A, MTB2A) have active LOW Power-Down
pin with internal 360k pull-down resistor and active HI Driver Enable
pin with internal 360k resistor. This would mean that power-down and
enable inputs would have ~2.3V on its input (above 2V) therefore driving
the back plane.
FIX: adding external 5k or smaller resistor to Power-down and
Driver-Enable pins.
[1]
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-v/arriav_handbook.pdf
(page 8-5)
[2] http://www.ti.com/lit/gpn/ds25cp102
[3] http://www.ti.com/lit/gpn/sn65mlvd040