• Jean-Paul Ricaud's avatar
    VHDL : corrected a mistake in the clock padding function. Output should · 0258cddf
    Jean-Paul Ricaud authored
    be a directe copy of the input when available without being clocking
    
     On branch development
    
    	modified:   fpga/sources/registers_init.vhdl
    	modified:   fpga/sources/src_clkpadding/clkpadding_top.vhdl
    	modified:   fpga/sources/testbench/clkpadding_tb.vhdl
    	modified:   pcb/gerber/Transcode Report.txt
    	modified:   sch/timex3_sch.pro
    0258cddf
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