• Jean-Paul Ricaud's avatar
    VHDL : added 5 kHzclock to padding function · b0272366
    Jean-Paul Ricaud authored
     On branch development
    
    	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
    	modified:   fpga/sources/src_clkpadding/clkpadding_config.txt
    	new file:   fpga/sources/src_clkpadding/clkpadding_padding.vhdl
    	modified:   fpga/sources/src_clkpadding/clkpadding_top.vhdl
    	modified:   fpga/sources/top.vhdl
    	modified:   pcb/gerber/Transcode Report.txt
    b0272366
Name
Last commit
Last update
..
fab Loading commit data...
gerber Loading commit data...
timex3_pcb.brd Loading commit data...
timex3_pcb.cmp Loading commit data...
timex3_pcb.net Loading commit data...
timex3_pcb.pro Loading commit data...