VHDL : corrected a bad pulse width in clock padding function 5kHz

On branch development modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/src_clkpadding/clkpadding_top.vhdl modified: fpga/sources/testbench/clkpadding_tb.vhdl

VHDL : corrected a bad pulse width in clock padding function 5kHz
On branch development modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/src_clkpadding/clkpadding_top.vhdl modified: fpga/sources/testbench/clkpadding_tb.vhdl
3b71443a · Jean-Paul Ricaud · e771a6d8 · 3b71443a · 3b71443a · 3b71443a
Commit 3b71443a authored Oct 04, 2018 by Jean-Paul Ricaud
Showing with 9661 additions and 9661 deletions

TimEX3_eeprom.mcs fpga/TimEX3/TimEX3_eeprom.mcs +9650 -9650

clkpadding_top.vhdl fpga/sources/src_clkpadding/clkpadding_top.vhdl +8 -8

clkpadding_tb.vhdl fpga/sources/testbench/clkpadding_tb.vhdl +3 -3

No files found.
--- a/fpga/TimEX3/TimEX3_eeprom.mcs
+++ b/fpga/TimEX3/TimEX3_eeprom.mcs
--- a/fpga/sources/src_clkpadding/clkpadding_top.vhdl
+++ b/fpga/sources/src_clkpadding/clkpadding_top.vhdl
@@ -81,8 +81,8 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
  ------------------------------------------------------------------------------
  -- signal
  ------------------------------------------------------------------------------
-  signal s_clkPADDING_LED_1khHz : std_logic;
-  signal s_clkPADDING_LED_5khHz : std_logic;
+  signal s_clkPADDING_LED_1kHz : std_logic := '0';
+  signal s_clkPADDING_LED_5kHz : std_logic := '0';

 ------------------------------------------------------------------------------
  --------------------------------- Main ---------------------------------------
@@ -95,14 +95,14 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
    g_gap_detect     => X"EA36", -- 59958 ; (59958 + 1) / 60e6 = 999.317 s
                                 -- 1 kHz period = 999.261 s
    g_padding_period => X"EA34", -- 59956 ; 59956 / 60e6 = 999.267 s
-    g_pulse_high     => X"2EE0")  -- 12000 => 200 s
+    g_pulse_high     => X"2EE0") -- 12000 => 200 s
  port map (
    p_clkPADDING_clk500mHz => p_clkPADDING_clk500mHz,
    p_clkPADDING_clk60MHz  => p_clkPADDING_clk60MHz,
    p_clkPADDING_clk_mon   => p_clkPADDING_1kHz_mon,  -- monitored clock
    p_clkPADDING_reset     => p_clkPADDING_reset,     -- global reset
    p_clkPADDING_outTTL    => p_clkPADDING_outTTL(2), -- TTL outputs ; output clock
-    p_clkPADDING_LED       => s_clkPADDING_LED_1khHz
+    p_clkPADDING_LED       => s_clkPADDING_LED_1kHz
  );

  -- 5kHz clock padding
@@ -111,14 +111,14 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
    g_gap_detect     => X"2ED2",  -- 11986 ; (11986 + 1) / 60e6 = 199.783 s
                                  -- 5 kHz period = 199.613 s
    g_padding_period => X"2EC9",  -- 11977 ; 11977 / 60e6 = 199.617 s
-    g_pulse_high     => X"2EE0" ) -- 12000 => 200 s
+    g_pulse_high     => X"1518")  -- 5400 => 90 s
  port map (
    p_clkPADDING_clk500mHz => p_clkPADDING_clk500mHz,
    p_clkPADDING_clk60MHz  => p_clkPADDING_clk60MHz,
    p_clkPADDING_clk_mon   => p_clkPADDING_5kHz_mon,  -- monitored clock
    p_clkPADDING_reset     => p_clkPADDING_reset,     -- global reset
    p_clkPADDING_outTTL    => p_clkPADDING_outTTL(3), -- TTL outputs ; output clock
-    p_clkPADDING_LED       => s_clkPADDING_LED_5khHz
+    p_clkPADDING_LED       => s_clkPADDING_LED_5kHz
  );

  ------------------------------------------------------------------------------
@@ -130,7 +130,7 @@ architecture rtl_clkPADDING_top of clkPADDING_top is

  p_clkPADDING_outPECL(4 downto 0) <= "00000";

-  p_clkPADDING_led(0) <= s_clkPADDING_LED_1khHz and s_clkPADDING_LED_5khHz; -- red LED
-  p_clkPADDING_led(1) <= '1'; -- green LED ON
+  p_clkPADDING_LED(0) <= s_clkPADDING_LED_1kHz and s_clkPADDING_LED_5kHz; -- red LED
+  p_clkPADDING_LED(1) <= '1'; -- green LED ON

 end architecture rtl_clkPADDING_top;
--- a/fpga/sources/testbench/clkpadding_tb.vhdl
+++ b/fpga/sources/testbench/clkpadding_tb.vhdl
@@ -7,7 +7,7 @@
 -- File     : clkPADDING_td.vhdl
 -- Revision : x.x.x
 -- Created  : July 19, 2014
-- Updated  : November 27, 2015
+-- Updated  : October 04, 2018
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -84,8 +84,8 @@ architecture simu_clkPADDING_tb of clkPADDING_tb is
    port map (
      p_clkPADDING_clk500mHz => s_clk500mHz,
      p_clkPADDING_clk60MHz  => s_clk60MHz,
-      p_clkPADDING_clk_mon   => s_clkTimBeL,
-      p_clkPADDING_aux_IN    => '0',
+      p_clkPADDING_1kHz_mon  => s_clkTimBeL,
+      p_clkPADDING_5kHz_mon  => '0',
      p_clkPADDING_reset     => s_reset,
      p_clkPADDING_outTTL    => s_clkoutTTL,
      p_clkPADDING_outPECL   => s_clkoutPECL,