Integer part is number of FPGA clocks (coarse counter).
13-bit fractional part.
With a 125MHz FPGA clock, LSB corresponds to 0.98ps.
Typical range: 268ms (using a <25.13>-bit value at 125MHz).
Number of coarse counter bits configurable with a VHDL generic.
Latency: 6 cycles at 125MHz (not including host interface module).
Configurable with a VHDL generic.
Calibration logic shared between channels.
Reports both rising and falling edges of the input signal.
Input signal must not have transitions shorter than three times the
FPGA clock period.
Uses a counter for coarse timing and a calibrated delay line for
Delay line implemented with carry chain (CARRY4) primitives.
at startup (and after receiving a reset command), send random
pulses into the delay line (coming from e.g. a on-chip ring
oscillator), build histogram, compute delays (as explained in
initialize the LUT, and measure the frequency of the
compensation ring oscillator.
for online temperature/voltage compensation, measure again the
frequency of the ring oscillator, compare it to the frequency
measured at start-up, linearly interpolate the delays, and
update the LUT.
"Wave union" not implemented.
Input signals (without host interface module):
Coarse counter reset.
Per-channel de-skew value.
Full reset (and recalibrate).
Output signals (without host interface module):
Startup calibration in progress.
Periodic counter overflow.
Received rising/falling edge notification:
Fixed point timestamp.
Raw encoded value from the delay line.
Forced switch to the calibration signal.
Access to the histogram values from the startup calibration.
Access to the frequencies of the online calibration ring