--------------------------------------------------------------------------------------- -- Title : Wishbone slave core for TDC --------------------------------------------------------------------------------------- -- File : tdc_wb.vhd -- Author : auto-generated by wbgen2 from tdc.wb -- Created : Tue Oct 25 16:54:19 2011 -- Standard : VHDL'87 --------------------------------------------------------------------------------------- -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc.wb -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! --------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wbgen2_pkg.all; entity tdc_wb is port ( rst_n_i : in std_logic; wb_clk_i : in std_logic; wb_addr_i : in std_logic_vector(5 downto 0); wb_data_i : in std_logic_vector(31 downto 0); wb_data_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_sel_i : in std_logic_vector(3 downto 0); wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_irq_o : out std_logic; -- Port for MONOSTABLE field: 'Reset' in reg: 'Control and status' tdc_cs_rst_o : out std_logic; -- Port for BIT field: 'Ready' in reg: 'Control and status' tdc_cs_rdy_i : in std_logic; -- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 0 (high word)' tdc_desh0_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 0 (low word)' tdc_desl0_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 1 (high word)' tdc_desh1_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 1 (low word)' tdc_desl1_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 2 (high word)' tdc_desh2_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 2 (low word)' tdc_desl2_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 3 (high word)' tdc_desh3_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 3 (low word)' tdc_desl3_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 4 (high word)' tdc_desh4_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 4 (low word)' tdc_desl4_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 5 (high word)' tdc_desh5_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 5 (low word)' tdc_desl5_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 6 (high word)' tdc_desh6_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 6 (low word)' tdc_desl6_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 7 (high word)' tdc_desh7_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 7 (low word)' tdc_desl7_o : out std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Detected polarities' tdc_pol_i : in std_logic_vector(7 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 0' tdc_raw0_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 0 (high word)' tdc_mesh0_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 0 (low word)' tdc_mesl0_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 1' tdc_raw1_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 1 (high word)' tdc_mesh1_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 1 (low word)' tdc_mesl1_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 2' tdc_raw2_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 2 (high word)' tdc_mesh2_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 2 (low word)' tdc_mesl2_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 3' tdc_raw3_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 3 (high word)' tdc_mesh3_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 3 (low word)' tdc_mesl3_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 4' tdc_raw4_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 4 (high word)' tdc_mesh4_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 4 (low word)' tdc_mesl4_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 5' tdc_raw5_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 5 (high word)' tdc_mesh5_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 5 (low word)' tdc_mesl5_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 6' tdc_raw6_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 6 (high word)' tdc_mesh6_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 6 (low word)' tdc_mesl6_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 7' tdc_raw7_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 7 (high word)' tdc_mesh7_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 7 (low word)' tdc_mesl7_i : in std_logic_vector(31 downto 0); irq_ie0_i : in std_logic; irq_ie1_i : in std_logic; irq_ie2_i : in std_logic; irq_ie3_i : in std_logic; irq_ie4_i : in std_logic; irq_ie5_i : in std_logic; irq_ie6_i : in std_logic; irq_ie7_i : in std_logic; irq_isc_i : in std_logic; irq_icc_i : in std_logic; -- Port for BIT field: 'Freeze request' in reg: 'Debug control' tdc_dctl_req_o : out std_logic; -- Port for BIT field: 'Freeze acknowledgement' in reg: 'Debug control' tdc_dctl_ack_i : in std_logic; -- Port for MONOSTABLE field: 'Switch to next channel' in reg: 'Channel selection' tdc_csel_next_o : out std_logic; -- Port for BIT field: 'Last channel reached' in reg: 'Channel selection' tdc_csel_last_i : in std_logic; -- Port for BIT field: 'Calibration signal select' in reg: 'Calibration signal selection' tdc_cal_o : out std_logic; -- Port for std_logic_vector field: 'Address' in reg: 'LUT read address' tdc_luta_o : out std_logic_vector(15 downto 0); -- Port for std_logic_vector field: 'Data' in reg: 'LUT read data' tdc_lutd_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Address' in reg: 'Histogram read address' tdc_hisa_o : out std_logic_vector(15 downto 0); -- Port for std_logic_vector field: 'Data' in reg: 'Histogram read data' tdc_hisd_i : in std_logic_vector(31 downto 0); -- Port for MONOSTABLE field: 'Measurement start' in reg: 'Frequency counter control and status' tdc_fcc_st_o : out std_logic; -- Port for BIT field: 'Measurement ready' in reg: 'Frequency counter control and status' tdc_fcc_rdy_i : in std_logic; -- Port for std_logic_vector field: 'Result' in reg: 'Frequency counter current value' tdc_fcr_i : in std_logic_vector(31 downto 0); -- Port for std_logic_vector field: 'Result' in reg: 'Frequency counter stored value' tdc_fcsr_i : in std_logic_vector(31 downto 0) ); end tdc_wb; architecture syn of tdc_wb is signal tdc_cs_rst_dly0 : std_logic ; signal tdc_cs_rst_int : std_logic ; signal tdc_desh0_int : std_logic_vector(31 downto 0); signal tdc_desl0_int : std_logic_vector(31 downto 0); signal tdc_desh1_int : std_logic_vector(31 downto 0); signal tdc_desl1_int : std_logic_vector(31 downto 0); signal tdc_desh2_int : std_logic_vector(31 downto 0); signal tdc_desl2_int : std_logic_vector(31 downto 0); signal tdc_desh3_int : std_logic_vector(31 downto 0); signal tdc_desl3_int : std_logic_vector(31 downto 0); signal tdc_desh4_int : std_logic_vector(31 downto 0); signal tdc_desl4_int : std_logic_vector(31 downto 0); signal tdc_desh5_int : std_logic_vector(31 downto 0); signal tdc_desl5_int : std_logic_vector(31 downto 0); signal tdc_desh6_int : std_logic_vector(31 downto 0); signal tdc_desl6_int : std_logic_vector(31 downto 0); signal tdc_desh7_int : std_logic_vector(31 downto 0); signal tdc_desl7_int : std_logic_vector(31 downto 0); signal tdc_dctl_req_int : std_logic ; signal tdc_csel_next_dly0 : std_logic ; signal tdc_csel_next_int : std_logic ; signal tdc_cal_int : std_logic ; signal tdc_luta_int : std_logic_vector(15 downto 0); signal tdc_hisa_int : std_logic_vector(15 downto 0); signal tdc_fcc_st_dly0 : std_logic ; signal tdc_fcc_st_int : std_logic ; signal eic_idr_int : std_logic_vector(9 downto 0); signal eic_idr_write_int : std_logic ; signal eic_ier_int : std_logic_vector(9 downto 0); signal eic_ier_write_int : std_logic ; signal eic_imr_int : std_logic_vector(9 downto 0); signal eic_isr_clear_int : std_logic_vector(9 downto 0); signal eic_isr_status_int : std_logic_vector(9 downto 0); signal eic_irq_ack_int : std_logic_vector(9 downto 0); signal eic_isr_write_int : std_logic ; signal irq_inputs_vector_int : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0); signal rddata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0); signal bwsel_reg : std_logic_vector(3 downto 0); signal rwaddr_reg : std_logic_vector(5 downto 0); signal ack_in_progress : std_logic ; signal wr_int : std_logic ; signal rd_int : std_logic ; signal bus_clock_int : std_logic ; signal allones : std_logic_vector(31 downto 0); signal allzeros : std_logic_vector(31 downto 0); begin -- Some internal signals assignments. For (foreseen) compatibility with other bus standards. wrdata_reg <= wb_data_i; bwsel_reg <= wb_sel_i; bus_clock_int <= wb_clk_i; rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i)); wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i); allones <= (others => '1'); allzeros <= (others => '0'); -- -- Main register bank access process. process (bus_clock_int, rst_n_i) begin if (rst_n_i = '0') then ack_sreg <= "0000000000"; ack_in_progress <= '0'; rddata_reg <= "00000000000000000000000000000000"; tdc_cs_rst_int <= '0'; tdc_desh0_int <= "00000000000000000000000000000000"; tdc_desl0_int <= "00000000000000000000000000000000"; tdc_desh1_int <= "00000000000000000000000000000000"; tdc_desl1_int <= "00000000000000000000000000000000"; tdc_desh2_int <= "00000000000000000000000000000000"; tdc_desl2_int <= "00000000000000000000000000000000"; tdc_desh3_int <= "00000000000000000000000000000000"; tdc_desl3_int <= "00000000000000000000000000000000"; tdc_desh4_int <= "00000000000000000000000000000000"; tdc_desl4_int <= "00000000000000000000000000000000"; tdc_desh5_int <= "00000000000000000000000000000000"; tdc_desl5_int <= "00000000000000000000000000000000"; tdc_desh6_int <= "00000000000000000000000000000000"; tdc_desl6_int <= "00000000000000000000000000000000"; tdc_desh7_int <= "00000000000000000000000000000000"; tdc_desl7_int <= "00000000000000000000000000000000"; tdc_dctl_req_int <= '0'; tdc_csel_next_int <= '0'; tdc_cal_int <= '0'; tdc_luta_int <= "0000000000000000"; tdc_hisa_int <= "0000000000000000"; tdc_fcc_st_int <= '0'; eic_idr_write_int <= '0'; eic_ier_write_int <= '0'; eic_isr_write_int <= '0'; elsif rising_edge(bus_clock_int) then -- advance the ACK generator shift register ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(9) <= '0'; if (ack_in_progress = '1') then if (ack_sreg(0) = '1') then tdc_cs_rst_int <= '0'; tdc_csel_next_int <= '0'; tdc_fcc_st_int <= '0'; eic_idr_write_int <= '0'; eic_ier_write_int <= '0'; eic_isr_write_int <= '0'; ack_in_progress <= '0'; else end if; else if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then case rwaddr_reg(5 downto 0) is when "000000" => if (wb_we_i = '1') then tdc_cs_rst_int <= wrdata_reg(0); rddata_reg(0) <= 'X'; rddata_reg(1) <= 'X'; else rddata_reg(0) <= 'X'; rddata_reg(1) <= tdc_cs_rdy_i; rddata_reg(2) <= 'X'; rddata_reg(3) <= 'X'; rddata_reg(4) <= 'X'; rddata_reg(5) <= 'X'; rddata_reg(6) <= 'X'; rddata_reg(7) <= 'X'; rddata_reg(8) <= 'X'; rddata_reg(9) <= 'X'; rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(2) <= '1'; ack_in_progress <= '1'; when "000001" => if (wb_we_i = '1') then tdc_desh0_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desh0_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "000010" => if (wb_we_i = '1') then tdc_desl0_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desl0_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "000011" => if (wb_we_i = '1') then tdc_desh1_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desh1_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "000100" => if (wb_we_i = '1') then tdc_desl1_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desl1_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "000101" => if (wb_we_i = '1') then tdc_desh2_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desh2_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "000110" => if (wb_we_i = '1') then tdc_desl2_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desl2_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "000111" => if (wb_we_i = '1') then tdc_desh3_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desh3_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "001000" => if (wb_we_i = '1') then tdc_desl3_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desl3_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "001001" => if (wb_we_i = '1') then tdc_desh4_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desh4_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "001010" => if (wb_we_i = '1') then tdc_desl4_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desl4_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "001011" => if (wb_we_i = '1') then tdc_desh5_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desh5_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "001100" => if (wb_we_i = '1') then tdc_desl5_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desl5_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "001101" => if (wb_we_i = '1') then tdc_desh6_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desh6_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "001110" => if (wb_we_i = '1') then tdc_desl6_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desl6_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "001111" => if (wb_we_i = '1') then tdc_desh7_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desh7_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "010000" => if (wb_we_i = '1') then tdc_desl7_int <= wrdata_reg(31 downto 0); else rddata_reg(31 downto 0) <= tdc_desl7_int; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "010001" => if (wb_we_i = '1') then else rddata_reg(7 downto 0) <= tdc_pol_i; rddata_reg(8) <= 'X'; rddata_reg(9) <= 'X'; rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "010010" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_raw0_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "010011" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesh0_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "010100" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesl0_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "010101" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_raw1_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "010110" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesh1_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "010111" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesl1_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "011000" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_raw2_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "011001" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesh2_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "011010" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesl2_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "011011" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_raw3_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "011100" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesh3_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "011101" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesl3_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "011110" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_raw4_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "011111" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesh4_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "100000" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesl4_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "100001" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_raw5_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "100010" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesh5_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "100011" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesl5_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "100100" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_raw6_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "100101" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesh6_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "100110" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesl6_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "100111" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_raw7_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "101000" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesh7_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "101001" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_mesl7_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "101010" => if (wb_we_i = '1') then rddata_reg(0) <= 'X'; tdc_dctl_req_int <= wrdata_reg(0); rddata_reg(1) <= 'X'; else rddata_reg(0) <= tdc_dctl_req_int; rddata_reg(1) <= tdc_dctl_ack_i; rddata_reg(2) <= 'X'; rddata_reg(3) <= 'X'; rddata_reg(4) <= 'X'; rddata_reg(5) <= 'X'; rddata_reg(6) <= 'X'; rddata_reg(7) <= 'X'; rddata_reg(8) <= 'X'; rddata_reg(9) <= 'X'; rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "101011" => if (wb_we_i = '1') then tdc_csel_next_int <= wrdata_reg(0); rddata_reg(0) <= 'X'; rddata_reg(1) <= 'X'; else rddata_reg(0) <= 'X'; rddata_reg(1) <= tdc_csel_last_i; rddata_reg(2) <= 'X'; rddata_reg(3) <= 'X'; rddata_reg(4) <= 'X'; rddata_reg(5) <= 'X'; rddata_reg(6) <= 'X'; rddata_reg(7) <= 'X'; rddata_reg(8) <= 'X'; rddata_reg(9) <= 'X'; rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(2) <= '1'; ack_in_progress <= '1'; when "101100" => if (wb_we_i = '1') then rddata_reg(0) <= 'X'; tdc_cal_int <= wrdata_reg(0); else rddata_reg(0) <= tdc_cal_int; rddata_reg(1) <= 'X'; rddata_reg(2) <= 'X'; rddata_reg(3) <= 'X'; rddata_reg(4) <= 'X'; rddata_reg(5) <= 'X'; rddata_reg(6) <= 'X'; rddata_reg(7) <= 'X'; rddata_reg(8) <= 'X'; rddata_reg(9) <= 'X'; rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "101101" => if (wb_we_i = '1') then tdc_luta_int <= wrdata_reg(15 downto 0); else rddata_reg(15 downto 0) <= tdc_luta_int; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "101110" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_lutd_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "101111" => if (wb_we_i = '1') then tdc_hisa_int <= wrdata_reg(15 downto 0); else rddata_reg(15 downto 0) <= tdc_hisa_int; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "110000" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_hisd_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "110001" => if (wb_we_i = '1') then tdc_fcc_st_int <= wrdata_reg(0); rddata_reg(0) <= 'X'; rddata_reg(1) <= 'X'; else rddata_reg(0) <= 'X'; rddata_reg(1) <= tdc_fcc_rdy_i; rddata_reg(2) <= 'X'; rddata_reg(3) <= 'X'; rddata_reg(4) <= 'X'; rddata_reg(5) <= 'X'; rddata_reg(6) <= 'X'; rddata_reg(7) <= 'X'; rddata_reg(8) <= 'X'; rddata_reg(9) <= 'X'; rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(2) <= '1'; ack_in_progress <= '1'; when "110010" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_fcr_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "110011" => if (wb_we_i = '1') then else rddata_reg(31 downto 0) <= tdc_fcsr_i; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "111000" => if (wb_we_i = '1') then eic_idr_write_int <= '1'; else rddata_reg(0) <= 'X'; rddata_reg(1) <= 'X'; rddata_reg(2) <= 'X'; rddata_reg(3) <= 'X'; rddata_reg(4) <= 'X'; rddata_reg(5) <= 'X'; rddata_reg(6) <= 'X'; rddata_reg(7) <= 'X'; rddata_reg(8) <= 'X'; rddata_reg(9) <= 'X'; rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "111001" => if (wb_we_i = '1') then eic_ier_write_int <= '1'; else rddata_reg(0) <= 'X'; rddata_reg(1) <= 'X'; rddata_reg(2) <= 'X'; rddata_reg(3) <= 'X'; rddata_reg(4) <= 'X'; rddata_reg(5) <= 'X'; rddata_reg(6) <= 'X'; rddata_reg(7) <= 'X'; rddata_reg(8) <= 'X'; rddata_reg(9) <= 'X'; rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "111010" => if (wb_we_i = '1') then else rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0); rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when "111011" => if (wb_we_i = '1') then eic_isr_write_int <= '1'; else rddata_reg(9 downto 0) <= eic_isr_status_int(9 downto 0); rddata_reg(10) <= 'X'; rddata_reg(11) <= 'X'; rddata_reg(12) <= 'X'; rddata_reg(13) <= 'X'; rddata_reg(14) <= 'X'; rddata_reg(15) <= 'X'; rddata_reg(16) <= 'X'; rddata_reg(17) <= 'X'; rddata_reg(18) <= 'X'; rddata_reg(19) <= 'X'; rddata_reg(20) <= 'X'; rddata_reg(21) <= 'X'; rddata_reg(22) <= 'X'; rddata_reg(23) <= 'X'; rddata_reg(24) <= 'X'; rddata_reg(25) <= 'X'; rddata_reg(26) <= 'X'; rddata_reg(27) <= 'X'; rddata_reg(28) <= 'X'; rddata_reg(29) <= 'X'; rddata_reg(30) <= 'X'; rddata_reg(31) <= 'X'; end if; ack_sreg(0) <= '1'; ack_in_progress <= '1'; when others => -- prevent the slave from hanging the bus on invalid address ack_in_progress <= '1'; ack_sreg(0) <= '1'; end case; end if; end if; end if; end process; -- Drive the data output bus wb_data_o <= rddata_reg; -- Reset process (bus_clock_int, rst_n_i) begin if (rst_n_i = '0') then tdc_cs_rst_dly0 <= '0'; tdc_cs_rst_o <= '0'; elsif rising_edge(bus_clock_int) then tdc_cs_rst_dly0 <= tdc_cs_rst_int; tdc_cs_rst_o <= tdc_cs_rst_int and (not tdc_cs_rst_dly0); end if; end process; -- Ready -- High word value tdc_desh0_o <= tdc_desh0_int; -- Low word value tdc_desl0_o <= tdc_desl0_int; -- High word value tdc_desh1_o <= tdc_desh1_int; -- Low word value tdc_desl1_o <= tdc_desl1_int; -- High word value tdc_desh2_o <= tdc_desh2_int; -- Low word value tdc_desl2_o <= tdc_desl2_int; -- High word value tdc_desh3_o <= tdc_desh3_int; -- Low word value tdc_desl3_o <= tdc_desl3_int; -- High word value tdc_desh4_o <= tdc_desh4_int; -- Low word value tdc_desl4_o <= tdc_desl4_int; -- High word value tdc_desh5_o <= tdc_desh5_int; -- Low word value tdc_desl5_o <= tdc_desl5_int; -- High word value tdc_desh6_o <= tdc_desh6_int; -- Low word value tdc_desl6_o <= tdc_desl6_int; -- High word value tdc_desh7_o <= tdc_desh7_int; -- Low word value tdc_desl7_o <= tdc_desl7_int; -- Value -- Value -- High word value -- Low word value -- Value -- High word value -- Low word value -- Value -- High word value -- Low word value -- Value -- High word value -- Low word value -- Value -- High word value -- Low word value -- Value -- High word value -- Low word value -- Value -- High word value -- Low word value -- Value -- High word value -- Low word value -- Freeze request tdc_dctl_req_o <= tdc_dctl_req_int; -- Freeze acknowledgement -- Switch to next channel process (bus_clock_int, rst_n_i) begin if (rst_n_i = '0') then tdc_csel_next_dly0 <= '0'; tdc_csel_next_o <= '0'; elsif rising_edge(bus_clock_int) then tdc_csel_next_dly0 <= tdc_csel_next_int; tdc_csel_next_o <= tdc_csel_next_int and (not tdc_csel_next_dly0); end if; end process; -- Last channel reached -- Calibration signal select tdc_cal_o <= tdc_cal_int; -- Address tdc_luta_o <= tdc_luta_int; -- Data -- Address tdc_hisa_o <= tdc_hisa_int; -- Data -- Measurement start process (bus_clock_int, rst_n_i) begin if (rst_n_i = '0') then tdc_fcc_st_dly0 <= '0'; tdc_fcc_st_o <= '0'; elsif rising_edge(bus_clock_int) then tdc_fcc_st_dly0 <= tdc_fcc_st_int; tdc_fcc_st_o <= tdc_fcc_st_int and (not tdc_fcc_st_dly0); end if; end process; -- Measurement ready -- Result -- Result -- extra code for reg/fifo/mem: Interrupt disable register eic_idr_int(9 downto 0) <= wrdata_reg(9 downto 0); -- extra code for reg/fifo/mem: Interrupt enable register eic_ier_int(9 downto 0) <= wrdata_reg(9 downto 0); -- extra code for reg/fifo/mem: Interrupt status register eic_isr_clear_int(9 downto 0) <= wrdata_reg(9 downto 0); -- extra code for reg/fifo/mem: IRQ_CONTROLLER eic_irq_controller_inst : wbgen2_eic generic map ( g_num_interrupts => 10, g_irq00_mode => 0, g_irq01_mode => 0, g_irq02_mode => 0, g_irq03_mode => 0, g_irq04_mode => 0, g_irq05_mode => 0, g_irq06_mode => 0, g_irq07_mode => 0, g_irq08_mode => 0, g_irq09_mode => 0, g_irq0a_mode => 0, g_irq0b_mode => 0, g_irq0c_mode => 0, g_irq0d_mode => 0, g_irq0e_mode => 0, g_irq0f_mode => 0, g_irq10_mode => 0, g_irq11_mode => 0, g_irq12_mode => 0, g_irq13_mode => 0, g_irq14_mode => 0, g_irq15_mode => 0, g_irq16_mode => 0, g_irq17_mode => 0, g_irq18_mode => 0, g_irq19_mode => 0, g_irq1a_mode => 0, g_irq1b_mode => 0, g_irq1c_mode => 0, g_irq1d_mode => 0, g_irq1e_mode => 0, g_irq1f_mode => 0 ) port map ( clk_i => bus_clock_int, rst_n_i => rst_n_i, irq_i => irq_inputs_vector_int, irq_ack_o => eic_irq_ack_int, reg_imr_o => eic_imr_int, reg_ier_i => eic_ier_int, reg_ier_wr_stb_i => eic_ier_write_int, reg_idr_i => eic_idr_int, reg_idr_wr_stb_i => eic_idr_write_int, reg_isr_o => eic_isr_status_int, reg_isr_i => eic_isr_clear_int, reg_isr_wr_stb_i => eic_isr_write_int, wb_irq_o => wb_irq_o ); irq_inputs_vector_int(0) <= irq_ie0_i; irq_inputs_vector_int(1) <= irq_ie1_i; irq_inputs_vector_int(2) <= irq_ie2_i; irq_inputs_vector_int(3) <= irq_ie3_i; irq_inputs_vector_int(4) <= irq_ie4_i; irq_inputs_vector_int(5) <= irq_ie5_i; irq_inputs_vector_int(6) <= irq_ie6_i; irq_inputs_vector_int(7) <= irq_ie7_i; irq_inputs_vector_int(8) <= irq_isc_i; irq_inputs_vector_int(9) <= irq_icc_i; rwaddr_reg <= wb_addr_i; -- ACK signal generation. Just pass the LSB of ACK counter. wb_ack_o <= ack_sreg(0); end syn;