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TDC core
Commit eeaac8b0 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
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Support for extra histogram bits

parent e04a047b
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Showing with 56 additions and 41 deletions
core/tdc.vhd
View file @ eeaac8b0
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-08-17 SB Created file -- 2011-08-17 SB Created file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -46,6 +47,8 @@ entity tdc is ...@@ -46,6 +47,8 @@ entity tdc is
g_RAW_COUNT : positive := 9; g_RAW_COUNT : positive := 9;
-- Number of fractional part bits. -- Number of fractional part bits.
g_FP_COUNT : positive := 13; g_FP_COUNT : positive := 13;
-- Number of extra histogram bits.
g_EXHIS_COUNT : positive := 4;
-- Number of coarse counter bits. -- Number of coarse counter bits.
g_COARSE_COUNT : positive := 25; g_COARSE_COUNT : positive := 25;
-- Length of each ring oscillator. -- Length of each ring oscillator.
...@@ -86,7 +89,7 @@ entity tdc is ...@@ -86,7 +89,7 @@ entity tdc is
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic; oc_start_i : in std_logic;
oc_ready_o : out std_logic; oc_ready_o : out std_logic;
oc_freq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0); oc_freq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
...@@ -112,8 +115,8 @@ signal c_raw : std_logic_vector(g_RAW_COUNT-1 downto 0); ...@@ -112,8 +115,8 @@ signal c_raw : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal his_a : std_logic_vector(g_RAW_COUNT-1 downto 0); signal his_a : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal his_a_c : std_logic_vector(g_RAW_COUNT-1 downto 0); signal his_a_c : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal his_we : std_logic; signal his_we : std_logic;
signal his_d_w : std_logic_vector(g_FP_COUNT-1 downto 0); signal his_d_w : std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
signal his_d_r : std_logic_vector(g_FP_COUNT-1 downto 0); signal his_d_r : std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
signal oc_start : std_logic; signal oc_start : std_logic;
signal oc_start_c : std_logic; signal oc_start_c : std_logic;
...@@ -130,6 +133,7 @@ begin ...@@ -130,6 +133,7 @@ begin
g_CARRY4_COUNT => g_CARRY4_COUNT, g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT, g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT, g_FP_COUNT => g_FP_COUNT,
g_EXHIS_COUNT => g_EXHIS_COUNT,
g_COARSE_COUNT => g_COARSE_COUNT, g_COARSE_COUNT => g_COARSE_COUNT,
g_RO_LENGTH => g_RO_LENGTH, g_RO_LENGTH => g_RO_LENGTH,
g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH, g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH,
...@@ -178,6 +182,7 @@ begin ...@@ -178,6 +182,7 @@ begin
generic map( generic map(
g_RAW_COUNT => g_RAW_COUNT, g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT, g_FP_COUNT => g_FP_COUNT,
g_EXHIS_COUNT => g_EXHIS_COUNT,
g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH
) )
port map( port map(
......
core/tdc_channelbank.vhd
View file @ eeaac8b0
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-25 SB Created file -- 2011-10-25 SB Created file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -47,6 +48,8 @@ entity tdc_channelbank is ...@@ -47,6 +48,8 @@ entity tdc_channelbank is
g_RAW_COUNT : positive; g_RAW_COUNT : positive;
-- Number of fractional part bits. -- Number of fractional part bits.
g_FP_COUNT : positive; g_FP_COUNT : positive;
-- Number of extra histogram bits.
g_EXHIS_COUNT : positive;
-- Number of coarse counter bits. -- Number of coarse counter bits.
g_COARSE_COUNT : positive; g_COARSE_COUNT : positive;
-- Length of each ring oscillator. -- Length of each ring oscillator.
...@@ -91,8 +94,8 @@ entity tdc_channelbank is ...@@ -91,8 +94,8 @@ entity tdc_channelbank is
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0); c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic; his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0); his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
-- Online calibration. -- Online calibration.
oc_start_i : in std_logic; oc_start_i : in std_logic;
...@@ -111,6 +114,7 @@ begin ...@@ -111,6 +114,7 @@ begin
g_CARRY4_COUNT => g_CARRY4_COUNT, g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT, g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT, g_FP_COUNT => g_FP_COUNT,
g_EXHIS_COUNT => g_EXHIS_COUNT,
g_COARSE_COUNT => g_COARSE_COUNT, g_COARSE_COUNT => g_COARSE_COUNT,
g_RO_LENGTH => g_RO_LENGTH, g_RO_LENGTH => g_RO_LENGTH,
g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH, g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH,
...@@ -162,6 +166,7 @@ begin ...@@ -162,6 +166,7 @@ begin
g_CARRY4_COUNT => g_CARRY4_COUNT, g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT, g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT, g_FP_COUNT => g_FP_COUNT,
g_EXHIS_COUNT => g_EXHIS_COUNT,
g_COARSE_COUNT => g_COARSE_COUNT, g_COARSE_COUNT => g_COARSE_COUNT,
g_RO_LENGTH => g_RO_LENGTH, g_RO_LENGTH => g_RO_LENGTH,
g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH, g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH,
......
core/tdc_channelbank_multi.vhd
View file @ eeaac8b0
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-25 SB Renamed to channelbank_multi -- 2011-10-25 SB Renamed to channelbank_multi
-- 2011-08-18 SB Added histogram -- 2011-08-18 SB Added histogram
-- 2011-08-17 SB Added frequency counter -- 2011-08-17 SB Added frequency counter
...@@ -55,21 +56,14 @@ use work.genram_pkg.all; ...@@ -55,21 +56,14 @@ use work.genram_pkg.all;
entity tdc_channelbank_multi is entity tdc_channelbank_multi is
generic( generic(
-- Number of channels.
g_CHANNEL_COUNT : positive; g_CHANNEL_COUNT : positive;
-- Number of CARRY4 elements per channel.
g_CARRY4_COUNT : positive; g_CARRY4_COUNT : positive;
-- Number of raw output bits.
g_RAW_COUNT : positive; g_RAW_COUNT : positive;
-- Number of fractional part bits.
g_FP_COUNT : positive; g_FP_COUNT : positive;
-- Number of coarse counter bits. g_EXHIS_COUNT : positive;
g_COARSE_COUNT : positive; g_COARSE_COUNT : positive;
-- Length of each ring oscillator.
g_RO_LENGTH : positive; g_RO_LENGTH : positive;
-- Frequency counter width.
g_FCOUNTER_WIDTH : positive; g_FCOUNTER_WIDTH : positive;
-- Frequency counter timer width.
g_FTIMER_WIDTH : positive g_FTIMER_WIDTH : positive
); );
port( port(
...@@ -107,8 +101,8 @@ entity tdc_channelbank_multi is ...@@ -107,8 +101,8 @@ entity tdc_channelbank_multi is
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0); c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic; his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0); his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
-- Online calibration. -- Online calibration.
oc_start_i : in std_logic; oc_start_i : in std_logic;
...@@ -180,7 +174,7 @@ begin ...@@ -180,7 +174,7 @@ begin
-- Histogram memory. -- Histogram memory.
cmp_histogram: generic_spram cmp_histogram: generic_spram
generic map( generic map(
g_data_width => g_FP_COUNT, g_data_width => g_FP_COUNT+g_EXHIS_COUNT,
g_size => g_CHANNEL_COUNT*2**g_RAW_COUNT, g_size => g_CHANNEL_COUNT*2**g_RAW_COUNT,
g_with_byte_enable => false, g_with_byte_enable => false,
g_init_file => "", g_init_file => "",
......
core/tdc_channelbank_single.vhd
View file @ eeaac8b0
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-25 SB Created file -- 2011-10-25 SB Created file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -39,19 +40,13 @@ use work.genram_pkg.all; ...@@ -39,19 +40,13 @@ use work.genram_pkg.all;
entity tdc_channelbank_single is entity tdc_channelbank_single is
generic( generic(
-- Number of CARRY4 elements per channel.
g_CARRY4_COUNT : positive; g_CARRY4_COUNT : positive;
-- Number of raw output bits.
g_RAW_COUNT : positive; g_RAW_COUNT : positive;
-- Number of fractional part bits.
g_FP_COUNT : positive; g_FP_COUNT : positive;
-- Number of coarse counter bits. g_EXHIS_COUNT : positive;
g_COARSE_COUNT : positive; g_COARSE_COUNT : positive;
-- Length of each ring oscillator.
g_RO_LENGTH : positive; g_RO_LENGTH : positive;
-- Frequency counter width.
g_FCOUNTER_WIDTH : positive; g_FCOUNTER_WIDTH : positive;
-- Frequency counter timer width.
g_FTIMER_WIDTH : positive g_FTIMER_WIDTH : positive
); );
port( port(
...@@ -89,8 +84,8 @@ entity tdc_channelbank_single is ...@@ -89,8 +84,8 @@ entity tdc_channelbank_single is
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0); c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic; his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0); his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
-- Online calibration. -- Online calibration.
oc_start_i : in std_logic; oc_start_i : in std_logic;
...@@ -150,7 +145,7 @@ begin ...@@ -150,7 +145,7 @@ begin
-- Histogram memory. -- Histogram memory.
cmp_histogram: generic_spram cmp_histogram: generic_spram
generic map( generic map(
g_data_width => g_FP_COUNT, g_data_width => g_FP_COUNT+g_EXHIS_COUNT,
g_size => 2**g_RAW_COUNT, g_size => 2**g_RAW_COUNT,
g_with_byte_enable => false, g_with_byte_enable => false,
g_init_file => "", g_init_file => "",
......
core/tdc_controller.vhd
View file @ eeaac8b0
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-27 SB Fix accumulator overflow -- 2011-10-27 SB Fix accumulator overflow
-- 2011-10-27 SB Fix LUT address offset -- 2011-10-27 SB Fix LUT address offset
-- 2011-08-19 SB Created file -- 2011-08-19 SB Created file
...@@ -44,6 +45,7 @@ entity tdc_controller is ...@@ -44,6 +45,7 @@ entity tdc_controller is
generic( generic(
g_RAW_COUNT : positive; g_RAW_COUNT : positive;
g_FP_COUNT : positive; g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_FCOUNTER_WIDTH : positive g_FCOUNTER_WIDTH : positive
); );
port( port(
...@@ -63,8 +65,8 @@ entity tdc_controller is ...@@ -63,8 +65,8 @@ entity tdc_controller is
c_raw_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); c_raw_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_o : out std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_o : out std_logic; his_we_o : out std_logic;
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0); his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_o : out std_logic; oc_start_o : out std_logic;
oc_ready_i : in std_logic; oc_ready_i : in std_logic;
...@@ -81,7 +83,7 @@ architecture rtl of tdc_controller is ...@@ -81,7 +83,7 @@ architecture rtl of tdc_controller is
signal ready_p: std_logic; signal ready_p: std_logic;
signal hc_count : std_logic_vector(g_FP_COUNT-1 downto 0); signal hc_count : std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
signal hc_reset : std_logic; signal hc_reset : std_logic;
signal hc_dec : std_logic; signal hc_dec : std_logic;
signal hc_zero : std_logic; signal hc_zero : std_logic;
...@@ -92,7 +94,7 @@ signal ha_inc : std_logic; ...@@ -92,7 +94,7 @@ signal ha_inc : std_logic;
signal ha_last : std_logic; signal ha_last : std_logic;
signal ha_sel : std_logic; signal ha_sel : std_logic;
signal acc : std_logic_vector(g_FP_COUNT-1 downto 0); signal acc : std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
signal acc_reset : std_logic; signal acc_reset : std_logic;
signal acc_en : std_logic; signal acc_en : std_logic;
...@@ -175,7 +177,9 @@ begin ...@@ -175,7 +177,9 @@ begin
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
mul <= std_logic_vector(unsigned(acc) * unsigned(oc_sfreq_i)); mul <= std_logic_vector(
unsigned(acc(g_FP_COUNT+g_EXHIS_COUNT-1 downto g_EXHIS_COUNT))
* unsigned(oc_sfreq_i));
mul_d1 <= mul; mul_d1 <= mul;
end if; end if;
end process; end process;
......
core/tdc_package.vhd
View file @ eeaac8b0
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-25 SB Added single/multi channel bank components -- 2011-10-25 SB Added single/multi channel bank components
-- 2011-08-03 SB Created file -- 2011-08-03 SB Created file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -43,6 +44,7 @@ component tdc is ...@@ -43,6 +44,7 @@ component tdc is
g_CARRY4_COUNT : positive := 100; g_CARRY4_COUNT : positive := 100;
g_RAW_COUNT : positive := 9; g_RAW_COUNT : positive := 9;
g_FP_COUNT : positive := 13; g_FP_COUNT : positive := 13;
g_EXHIS_COUNT : positive := 4;
g_COARSE_COUNT : positive := 25; g_COARSE_COUNT : positive := 25;
g_RO_LENGTH : positive := 20; g_RO_LENGTH : positive := 20;
g_FCOUNTER_WIDTH : positive := 13; g_FCOUNTER_WIDTH : positive := 13;
...@@ -74,7 +76,7 @@ component tdc is ...@@ -74,7 +76,7 @@ component tdc is
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic; oc_start_i : in std_logic;
oc_ready_o : out std_logic; oc_ready_o : out std_logic;
oc_freq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0); oc_freq_o : out std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
...@@ -86,6 +88,7 @@ component tdc_controller is ...@@ -86,6 +88,7 @@ component tdc_controller is
generic( generic(
g_RAW_COUNT : positive; g_RAW_COUNT : positive;
g_FP_COUNT : positive; g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_FCOUNTER_WIDTH : positive g_FCOUNTER_WIDTH : positive
); );
port( port(
...@@ -105,8 +108,8 @@ component tdc_controller is ...@@ -105,8 +108,8 @@ component tdc_controller is
c_raw_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); c_raw_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_o : out std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_o : out std_logic; his_we_o : out std_logic;
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0); his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_o : out std_logic; oc_start_o : out std_logic;
oc_ready_i : in std_logic; oc_ready_i : in std_logic;
...@@ -125,6 +128,7 @@ component tdc_channelbank is ...@@ -125,6 +128,7 @@ component tdc_channelbank is
g_CARRY4_COUNT : positive; g_CARRY4_COUNT : positive;
g_RAW_COUNT : positive; g_RAW_COUNT : positive;
g_FP_COUNT : positive; g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_COARSE_COUNT : positive; g_COARSE_COUNT : positive;
g_RO_LENGTH : positive; g_RO_LENGTH : positive;
g_FCOUNTER_WIDTH : positive; g_FCOUNTER_WIDTH : positive;
...@@ -159,8 +163,8 @@ component tdc_channelbank is ...@@ -159,8 +163,8 @@ component tdc_channelbank is
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0); c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic; his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0); his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic; oc_start_i : in std_logic;
oc_ready_o : out std_logic; oc_ready_o : out std_logic;
...@@ -175,6 +179,7 @@ component tdc_channelbank_single is ...@@ -175,6 +179,7 @@ component tdc_channelbank_single is
g_CARRY4_COUNT : positive; g_CARRY4_COUNT : positive;
g_RAW_COUNT : positive; g_RAW_COUNT : positive;
g_FP_COUNT : positive; g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_COARSE_COUNT : positive; g_COARSE_COUNT : positive;
g_RO_LENGTH : positive; g_RO_LENGTH : positive;
g_FCOUNTER_WIDTH : positive; g_FCOUNTER_WIDTH : positive;
...@@ -209,8 +214,8 @@ component tdc_channelbank_single is ...@@ -209,8 +214,8 @@ component tdc_channelbank_single is
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0); c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic; his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0); his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic; oc_start_i : in std_logic;
oc_ready_o : out std_logic; oc_ready_o : out std_logic;
...@@ -226,6 +231,7 @@ component tdc_channelbank_multi is ...@@ -226,6 +231,7 @@ component tdc_channelbank_multi is
g_CARRY4_COUNT : positive; g_CARRY4_COUNT : positive;
g_RAW_COUNT : positive; g_RAW_COUNT : positive;
g_FP_COUNT : positive; g_FP_COUNT : positive;
g_EXHIS_COUNT : positive;
g_COARSE_COUNT : positive; g_COARSE_COUNT : positive;
g_RO_LENGTH : positive; g_RO_LENGTH : positive;
g_FCOUNTER_WIDTH : positive; g_FCOUNTER_WIDTH : positive;
...@@ -260,8 +266,8 @@ component tdc_channelbank_multi is ...@@ -260,8 +266,8 @@ component tdc_channelbank_multi is
c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0); c_raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0); his_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
his_we_i : in std_logic; his_we_i : in std_logic;
his_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0); his_d_i : in std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
his_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0); his_d_o : out std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
oc_start_i : in std_logic; oc_start_i : in std_logic;
oc_ready_o : out std_logic; oc_ready_o : out std_logic;
......
demo/boards/spec/rtl/system.v
View file @ eeaac8b0
...@@ -478,6 +478,7 @@ tdc_hostif #( ...@@ -478,6 +478,7 @@ tdc_hostif #(
.g_CARRY4_COUNT(124), .g_CARRY4_COUNT(124),
.g_RAW_COUNT(9), .g_RAW_COUNT(9),
.g_FP_COUNT(13), .g_FP_COUNT(13),
.g_EXHIS_COUNT(5),
.g_COARSE_COUNT(25), .g_COARSE_COUNT(25),
.g_RO_LENGTH(31), .g_RO_LENGTH(31),
.g_FCOUNTER_WIDTH(13), .g_FCOUNTER_WIDTH(13),
......
hostif/tdc_hostif.vhd
View file @ eeaac8b0
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-08-27 SB Reduced supported channel count to 8 -- 2011-08-27 SB Reduced supported channel count to 8
-- 2011-08-26 SB Created file -- 2011-08-26 SB Created file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -44,6 +45,7 @@ entity tdc_hostif is ...@@ -44,6 +45,7 @@ entity tdc_hostif is
g_CARRY4_COUNT : positive := 124; g_CARRY4_COUNT : positive := 124;
g_RAW_COUNT : positive := 9; g_RAW_COUNT : positive := 9;
g_FP_COUNT : positive := 13; g_FP_COUNT : positive := 13;
g_EXHIS_COUNT : positive := 4;
g_COARSE_COUNT : positive := 25; g_COARSE_COUNT : positive := 25;
g_RO_LENGTH : positive := 31; g_RO_LENGTH : positive := 31;
g_FCOUNTER_WIDTH : positive := 13; g_FCOUNTER_WIDTH : positive := 13;
...@@ -87,7 +89,7 @@ signal calib_sel : std_logic; ...@@ -87,7 +89,7 @@ signal calib_sel : std_logic;
signal lut_a : std_logic_vector(g_RAW_COUNT-1 downto 0); signal lut_a : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal lut_d : std_logic_vector(g_FP_COUNT-1 downto 0); signal lut_d : std_logic_vector(g_FP_COUNT-1 downto 0);
signal his_a : std_logic_vector(g_RAW_COUNT-1 downto 0); signal his_a : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal his_d : std_logic_vector(g_FP_COUNT-1 downto 0); signal his_d : std_logic_vector(g_FP_COUNT+g_EXHIS_COUNT-1 downto 0);
signal oc_start : std_logic; signal oc_start : std_logic;
signal oc_ready : std_logic; signal oc_ready : std_logic;
signal oc_freq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0); signal oc_freq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
...@@ -115,6 +117,7 @@ begin ...@@ -115,6 +117,7 @@ begin
g_CARRY4_COUNT => g_CARRY4_COUNT, g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT, g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT, g_FP_COUNT => g_FP_COUNT,
g_EXHIS_COUNT => g_EXHIS_COUNT,
g_COARSE_COUNT => g_COARSE_COUNT, g_COARSE_COUNT => g_COARSE_COUNT,
g_RO_LENGTH => g_RO_LENGTH, g_RO_LENGTH => g_RO_LENGTH,
g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH, g_FCOUNTER_WIDTH => g_FCOUNTER_WIDTH,
......
hostif/tdc_hostif_package.vhd
View file @ eeaac8b0
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-08-27 SB Reduced supported channel count to 8 -- 2011-08-27 SB Reduced supported channel count to 8
-- 2011-08-25 SB Created file -- 2011-08-25 SB Created file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -44,6 +45,7 @@ component tdc_hostif is ...@@ -44,6 +45,7 @@ component tdc_hostif is
g_CARRY4_COUNT : positive := 100; g_CARRY4_COUNT : positive := 100;
g_RAW_COUNT : positive := 9; g_RAW_COUNT : positive := 9;
g_FP_COUNT : positive := 13; g_FP_COUNT : positive := 13;
g_EXHIS_COUNT : positive := 4;
g_COARSE_COUNT : positive := 25; g_COARSE_COUNT : positive := 25;
g_RO_LENGTH : positive := 20; g_RO_LENGTH : positive := 20;
g_FCOUNTER_WIDTH : positive := 13; g_FCOUNTER_WIDTH : positive := 13;
......
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