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TDC core
Commit cd65f5f7 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
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demo: integrate TDC core

parent d81eb4a0
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Showing with 106 additions and 23 deletions
demo/boards/spec/rtl/system.v
View file @ cd65f5f7
...@@ -28,7 +28,11 @@ module system( ...@@ -28,7 +28,11 @@ module system(
// GPIO // GPIO
input [2:0] btn, input [2:0] btn,
output [1:0] led output [1:0] led,
// TDC
input [4:0] tdc_signal,
input [4:0] tdc_calib
); );
//------------------------------------------------------------------ //------------------------------------------------------------------
...@@ -98,7 +102,8 @@ wire cpuibus_ack, ...@@ -98,7 +102,8 @@ wire cpuibus_ack,
wire [31:0] brg_adr, wire [31:0] brg_adr,
bram_adr, bram_adr,
sram_adr, sram_adr,
csrbrg_adr; csrbrg_adr,
tdc_adr;
wire [2:0] brg_cti, wire [2:0] brg_cti,
bram_cti, bram_cti,
...@@ -108,25 +113,32 @@ wire [31:0] bram_dat_r, ...@@ -108,25 +113,32 @@ wire [31:0] bram_dat_r,
sram_dat_r, sram_dat_r,
sram_dat_w, sram_dat_w,
csrbrg_dat_r, csrbrg_dat_r,
csrbrg_dat_w; csrbrg_dat_w,
tdc_dat_r,
tdc_dat_w;
wire [3:0] bram_sel, wire [3:0] bram_sel,
sram_sel; sram_sel,
tdc_sel;
wire csrbrg_we, wire csrbrg_we,
aceusb_we; sram_we,
tdc_we;
wire bram_cyc, wire bram_cyc,
sram_cyc, sram_cyc,
csrbrg_cyc; csrbrg_cyc,
tdc_cyc;
wire bram_stb, wire bram_stb,
sram_stb, sram_stb,
csrbrg_stb; csrbrg_stb,
tdc_stb;
wire bram_ack, wire bram_ack,
sram_ack, sram_ack,
csrbrg_ack; csrbrg_ack,
tdc_ack;
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// Wishbone switch // Wishbone switch
...@@ -137,7 +149,8 @@ conbus #( ...@@ -137,7 +149,8 @@ conbus #(
.s1_addr(3'b001), // free 0x20000000 .s1_addr(3'b001), // free 0x20000000
.s2_addr(3'b010), // sram 0x40000000 .s2_addr(3'b010), // sram 0x40000000
.s3_addr(3'b100), // CSR bridge 0x80000000 .s3_addr(3'b100), // CSR bridge 0x80000000
.s4_addr(3'b101) // free 0xa0000000 .s4_addr(3'b101), // TDC 0xa0000000
.s5_addr(3'b110), // free 0xc0000000
) conbus ( ) conbus (
.sys_clk(sys_clk), .sys_clk(sys_clk),
.sys_rst(sys_rst), .sys_rst(sys_rst),
...@@ -192,6 +205,16 @@ conbus #( ...@@ -192,6 +205,16 @@ conbus #(
.m4_cyc_i(1'b0), .m4_cyc_i(1'b0),
.m4_stb_i(1'b0), .m4_stb_i(1'b0),
.m4_ack_o(), .m4_ack_o(),
// Master 5
.m5_dat_i(32'bx),
.m5_dat_o(),
.m5_adr_i(32'bx),
.m5_cti_i(3'bx),
.m5_we_i(1'bx),
.m5_sel_i(4'bx),
.m5_cyc_i(1'b0),
.m5_stb_i(1'b0),
.m5_ack_o(),
// Slave 0 // Slave 0
.s0_dat_i(bram_dat_r), .s0_dat_i(bram_dat_r),
...@@ -228,13 +251,20 @@ conbus #( ...@@ -228,13 +251,20 @@ conbus #(
.s3_stb_o(csrbrg_stb), .s3_stb_o(csrbrg_stb),
.s3_ack_i(csrbrg_ack), .s3_ack_i(csrbrg_ack),
// Slave 4 // Slave 4
.s4_dat_i(32'bx), .s4_dat_i(tdc_dat_r),
.s4_dat_o(), .s4_dat_o(tdc_dat_w),
.s4_adr_o(), .s4_adr_o(tdc_adr),
.s4_we_o(), .s4_we_o(tdc_we),
.s4_cyc_o(), .s4_cyc_o(tdc_cyc),
.s4_stb_o(), .s4_stb_o(tdc_stb),
.s4_ack_i(1'b0) .s4_sel_o(tdc_sel),
.s4_ack_i(tdc_ack),
// Slave 5
.s5_dat_i(32'bx),
.s5_adr_o(),
.s5_cyc_o(),
.s5_stb_o(),
.s5_ack_i(1'b0)
); );
//------------------------------------------------------------------ //------------------------------------------------------------------
...@@ -279,9 +309,11 @@ wire timer0_irq; ...@@ -279,9 +309,11 @@ wire timer0_irq;
wire timer1_irq; wire timer1_irq;
wire uartrx_irq; wire uartrx_irq;
wire uarttx_irq; wire uarttx_irq;
wire tdc_irq;
wire [31:0] cpu_interrupt; wire [31:0] cpu_interrupt;
assign cpu_interrupt = {27'd0, assign cpu_interrupt = {26'd0,
tdc_irq,
uarttx_irq, uarttx_irq,
uartrx_irq, uartrx_irq,
timer1_irq, timer1_irq,
...@@ -337,7 +369,7 @@ bram #( ...@@ -337,7 +369,7 @@ bram #(
.wb_adr_i(bram_adr), .wb_adr_i(bram_adr),
.wb_dat_o(bram_dat_r), .wb_dat_o(bram_dat_r),
.wb_dat_i(), .wb_dat_i(32'bx),
.wb_sel_i(bram_sel), .wb_sel_i(bram_sel),
.wb_stb_i(bram_stb), .wb_stb_i(bram_stb),
.wb_cyc_i(bram_cyc), .wb_cyc_i(bram_cyc),
...@@ -387,8 +419,6 @@ uart #( ...@@ -387,8 +419,6 @@ uart #(
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// System Controller // System Controller
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
wire [13:0] gpio_outputs;
sysctl #( sysctl #(
.csr_addr(4'h1), .csr_addr(4'h1),
.ninputs(3), .ninputs(3),
...@@ -413,4 +443,36 @@ sysctl #( ...@@ -413,4 +443,36 @@ sysctl #(
.hard_reset(hard_reset) .hard_reset(hard_reset)
); );
//---------------------------------------------------------------------------
// TDC
//---------------------------------------------------------------------------
tdc_hostif #(
.g_CHANNEL_COUNT(5),
.g_CARRY4_COUNT(100),
.g_RAW_COUNT(9),
.g_FP_COUNT(13),
.g_COARSE_COUNT(25),
.g_RO_LENGTH(20),
.g_FCOUNTER_WIDTH(13),
.g_FTIMER_WIDTH(10)
) tdc (
.rst_n_i(~sys_rst),
.wb_clk_i(sys_clk),
.wb_addr_i(tdc_adr[5:0]),
.wb_data_i(tdc_dat_w),
.wb_data_o(tdc_dat_r),
.wb_cyc_i(tdc_cyc),
.wb_sel_i(tdc_sel),
.wb_stb_i(tdc_stb),
.wb_we_i(tdc_we),
.wb_ack_o(tdc_ack),
.wb_irq_o(tdc_irq),
.cc_rst_i(1'b0),
.cc_cy_o(),
.signal_i(tdc_signal),
.calib_i(tdc_calib)
);
endmodule endmodule
demo/boards/spec/sources.mak
View file @ cd65f5f7
...@@ -18,3 +18,10 @@ UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v) ...@@ -18,3 +18,10 @@ UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v)
SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v) SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(CSRBRG_SRC) $(BRAM_SRC) $(UART_SRC) $(SYSCTL_SRC) CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(CSRBRG_SRC) $(BRAM_SRC) $(UART_SRC) $(SYSCTL_SRC)
TDC_SRC=$(wildcard $(TDC_DIR)/core/*.vhd)
TDCHI_SRC=$(wildcard $(TDC_DIR)/hostif/*.vhd)
GENRAMS_SRC=$(wildcard $(GENCORES_DIR)/modules/genrams/*.vhd) $(wildcard $(GENCORES_DIR)/modules/genrams/xilinx/*.vhd)
WBGEN_SRC=$(wildcard $(WBGEN_DIR)/lib/*.vhd)
CORES_SRC_VHDL=$(GENRAMS_SRC) $(WBGEN_SRC) $(TDC_SRC) $(TDCHI_SRC)
demo/boards/spec/synthesis/Makefile.xst
View file @ cd65f5f7
BOARD_DIR=../rtl BOARD_DIR=../rtl
CORES_DIR=../../../cores CORES_DIR=../../../cores
GENCORES_DIR=../../../../../general-cores
WBGEN_DIR=../../../../../wishbone-gen
TDC_DIR=../../../..
include ../sources.mak include ../sources.mak
SRC=$(BOARD_SRC) $(CORES_SRC) SRC=$(BOARD_SRC) $(CORES_SRC)
SRC_VHDL=$(CORES_SRC_VHDL)
all: build/system.bit all: build/system.bit
build/system.ucf: common.ucf xst.ucf build/system.ucf: common.ucf xst.ucf
cat common.ucf xst.ucf > build/system.ucf cat common.ucf xst.ucf > build/system.ucf
build/system.prj: $(SRC) build/system.prj: $(SRC) $(SRC_VHDL)
rm -f build/system.prj rm -f build/system.prj
for i in `echo $^`; do \ for i in `echo $(SRC)`; do \
echo "verilog work ../$$i" >> build/system.prj; \ echo "verilog work ../$$i" >> build/system.prj; \
done
for i in `echo $(SRC_VHDL)`; do \
echo "vhdl work ../$$i" >> build/system.prj; \
done done
build/system.ngc: build/system.prj build/system.ngc: build/system.prj
......
demo/boards/spec/synthesis/common.ucf
View file @ cd65f5f7
# ==== Clock input ==== # ==== Clock input ====
NET "clkin" TNM_NET = CLK_125MHZ; NET "clkin" TNM_NET = CLK_125MHZ;
TIMESPEC TS_CLK_125MHZ = PERIOD CLK_125MHZ 8 ns; TIMESPEC TS_CLK_125MHZ = PERIOD CLK_125MHZ 8 ns;
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[0].cmp_channel/muxed_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[1].cmp_channel/muxed_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[2].cmp_channel/muxed_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[3].cmp_channel/muxed_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[4].cmp_channel/muxed_signal" TIG;
demo/software/include/hw/interrupts.h
View file @ cd65f5f7
...@@ -23,5 +23,6 @@ ...@@ -23,5 +23,6 @@
#define IRQ_TIMER1 (0x00000004) #define IRQ_TIMER1 (0x00000004)
#define IRQ_UARTRX (0x00000008) #define IRQ_UARTRX (0x00000008)
#define IRQ_UARTTX (0x00000010) #define IRQ_UARTTX (0x00000010)
#define IRQ_TDC (0x00000020)
#endif /* __INTERRUPTS_H */ #endif /* __INTERRUPTS_H */
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