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TDC core
Commits
b1c504ad
Commit
b1c504ad
authored
Oct 28, 2011
by
Sebastien Bourdeauducq
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delayline: reorder taps by increasing delays
parent
e9cd30b6
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5 changed files
with
632 additions
and
9 deletions
+632
-9
tdc_channel.vhd
core/tdc_channel.vhd
+0
-2
tdc_delayline.vhd
core/tdc_delayline.vhd
+16
-4
tdc_ordertaps.vhd
core/tdc_ordertaps.vhd
+521
-0
tdc_package.vhd
core/tdc_package.vhd
+13
-3
ordertaps.py
ordertaps.py
+82
-0
No files found.
core/tdc_channel.vhd
View file @
b1c504ad
...
@@ -122,8 +122,6 @@ begin
...
@@ -122,8 +122,6 @@ begin
taps_o
=>
taps
taps_o
=>
taps
);
);
-- TODO: reorder bits by increasing delays
cmp_lbc
:
tdc_lbc
cmp_lbc
:
tdc_lbc
generic
map
(
generic
map
(
g_N
=>
g_RAW_COUNT
,
g_N
=>
g_RAW_COUNT
,
...
...
core/tdc_delayline.vhd
View file @
b1c504ad
...
@@ -61,9 +61,10 @@ entity tdc_delayline is
...
@@ -61,9 +61,10 @@ entity tdc_delayline is
end
entity
;
end
entity
;
architecture
rtl
of
tdc_delayline
is
architecture
rtl
of
tdc_delayline
is
signal
unreg_rev
:
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
);
signal
unreg_rev
:
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
);
signal
reg1_rev
:
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
);
signal
reg1_rev
:
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
);
signal
taps_rev
:
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
);
signal
taps_rev
:
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
);
signal
taps_rev_sorted
:
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
);
function
f_bit_reverse
(
s
:
std_logic_vector
)
return
std_logic_vector
is
function
f_bit_reverse
(
s
:
std_logic_vector
)
return
std_logic_vector
is
variable
v_r
:
std_logic_vector
(
s
'high
downto
s
'low
);
variable
v_r
:
std_logic_vector
(
s
'high
downto
s
'low
);
...
@@ -121,5 +122,16 @@ begin
...
@@ -121,5 +122,16 @@ begin
);
);
end
generate
;
end
generate
;
taps_o
<=
f_bit_reverse
(
taps_rev
);
-- sort taps by increasing delays, according to static timing model
cmp_ordertaps
:
tdc_ordertaps
generic
map
(
g_WIDTH
=>
g_WIDTH
)
port
map
(
unsorted_i
=>
taps_rev
,
sorted_o
=>
taps_rev_sorted
);
-- sort output with the least delay in the most significant bit
taps_o
<=
f_bit_reverse
(
taps_rev_sorted
);
end
architecture
;
end
architecture
;
core/tdc_ordertaps.vhd
0 → 100644
View file @
b1c504ad
This diff is collapsed.
Click to expand it.
core/tdc_package.vhd
View file @
b1c504ad
...
@@ -333,8 +333,8 @@ end component;
...
@@ -333,8 +333,8 @@ end component;
component
tdc_lbc
is
component
tdc_lbc
is
generic
(
generic
(
g_N
:
positive
;
g_N
:
positive
;
g_NIN
:
positive
g_NIN
:
positive
);
);
port
(
port
(
clk_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
...
@@ -347,7 +347,7 @@ end component;
...
@@ -347,7 +347,7 @@ end component;
component
tdc_delayline
is
component
tdc_delayline
is
generic
(
generic
(
g_WIDTH
:
positive
g_WIDTH
:
positive
);
);
port
(
port
(
clk_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
...
@@ -357,6 +357,16 @@ component tdc_delayline is
...
@@ -357,6 +357,16 @@ component tdc_delayline is
);
);
end
component
;
end
component
;
component
tdc_ordertaps
is
generic
(
g_WIDTH
:
positive
);
port
(
unsorted_i
:
in
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
);
sorted_o
:
out
std_logic_vector
(
4
*
g_WIDTH
-1
downto
0
)
);
end
component
;
component
tdc_divider
is
component
tdc_divider
is
generic
(
generic
(
g_WIDTH
:
positive
g_WIDTH
:
positive
...
...
ordertaps.py
0 → 100755
View file @
b1c504ad
#!/usr/bin/python
# This program creates a VHDL entity that sorts the taps of the delay line
# by increasing delays, according to the Xilinx static timing model.
#
# 1. Create a design in ISE with the delay line only, for the targeted FPGA.
# If you run out of I/Os, connect some dummy logic to the taps to prevent
# optimizations. Use this Verilog source for example:
#module top(
# input clk_i,
# input reset_i,
# input signal_i,
# output xtap
#);
#
#wire [124*4-1:0] taps;
#
#tdc_delayline #(
# .g_WIDTH(124)
#) dl (
# .clk_i(clk_i),
# .reset_i(reset_i),
# .signal_i(signal_i),
# .taps_o(taps)
#);
#
#assign xtap = |taps;
#
#endmodule
# 2. Apply this UCF constraint:
# NET "signal_i" OFFSET=IN 20 ns BEFORE "clk_i";
# 3. Implement the design.
# 4. Generate the XML timing report (.twx): trce -v 1000 top.ncd
# 5. Process it with this program.
from
xml.etree.ElementTree
import
ElementTree
import
re
filename
=
"top.twx"
ucftime
=
20.0
delays
=
[]
tree
=
ElementTree
()
tree
.
parse
(
filename
)
paths
=
tree
.
findall
(
"twBody/twVerboseRpt/twConst/twPathRpt"
)
for
path
in
paths
:
dest
=
path
.
find
(
"twConstOffIn/twDest"
)
.
text
slack
=
path
.
find
(
"twConstOffIn/twSlack"
)
.
text
destn
=
int
(
re
.
split
(
"
\
[|
\
]"
,
dest
)[
1
])
time
=
ucftime
-
float
(
slack
)
delays
.
append
((
destn
,
time
))
sdelays
=
sorted
(
delays
,
key
=
lambda
dd
:
dd
[
1
])
print
"""
-- This file was autogenerated by ordertaps.py
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tdc_package.all;
entity tdc_ordertaps is
generic(
g_WIDTH: positive
);
port(
unsorted_i : in std_logic_vector(4*g_WIDTH-1 downto 0);
sorted_o : out std_logic_vector(4*g_WIDTH-1 downto 0)
);
end entity;
architecture rtl of tdc_ordertaps is
begin
"""
i
=
0
for
tap
in
sdelays
:
print
" sorted_o(
%
d) <= unsorted_i(
%
d); --
%.3
f ns"
%
(
i
,
tap
[
0
],
tap
[
1
])
i
=
i
+
1
print
"""
end architecture;
"""
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