Frequency counter test bench

adf29743 · Sebastien Bourdeauducq · 30f0ec5f · adf29743 · adf29743 · adf29743
Commit adf29743 authored Aug 17, 2011 by Sebastien Bourdeauducq
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tdc_freqc.vhd core/tdc_freqc.vhd +6 -6

tdc_package.vhd core/tdc_package.vhd +16 -0

simulate.sh tb/freqc/simulate.sh +5 -0

tb_freqc.vhd tb/freqc/tb_freqc.vhd +119 -0

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--- a/core/tdc_freqc.vhd
+++ b/core/tdc_freqc.vhd
--- a/core/tdc_package.vhd
+++ b/core/tdc_package.vhd
@@ -22,6 +22,22 @@ use ieee.std_logic_1164.all;

 package tdc_package is

+component tdc_freqc is
+    generic(
+        g_COUNTER_WIDTH : positive;
+        g_TIMER_WIDTH   : positive
+    );
+    port(
+        clk_i   : in std_logic;
+        reset_i : in std_logic;
+        
+        clk_m_i : in std_logic;
+        start_i : in std_logic;
+        ready_o : out std_logic;
+        freq_o  : out std_logic_vector(g_COUNTER_WIDTH-1 downto 0)
+    );
+end component;
+
 component tdc_channelbank is
    generic(
        g_CHANNEL_COUNT : positive;

--- a/tb/freqc/simulate.sh
+++ b/tb/freqc/simulate.sh
+#!/bin/sh
+set -e
+ghdl -i ../../core/tdc_package.vhd ../../core/tdc_psync.vhd ../../core/tdc_freqc.vhd tb_freqc.vhd
+ghdl -m tb_freqc
+ghdl -r tb_freqc
--- a/tb/freqc/tb_freqc.vhd
+++ b/tb/freqc/tb_freqc.vhd
+-------------------------------------------------------------------------------
+-- TDC Core / CERN
+-------------------------------------------------------------------------------
+--
+-- unit name: tb_lbc
+--
+-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
+--
+-- description: Test bench for frequency counter
+--
+-- references: http://www.ohwr.org/projects/tdc-core
+--
+-------------------------------------------------------------------------------
+-- last changes:
+-- 2011-08-17 SB Created file
+-------------------------------------------------------------------------------
+
+-- Copyright (C) 2011 Sebastien Bourdeauducq
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+library work;
+use work.tdc_package.all;
+
+entity tb_freqc is
+    generic(
+        g_COUNTER_WIDTH : positive := 20;
+        g_TIMER_WIDTH   : positive := 16;
+        g_CLK_PERIOD    : real := 8.0;
+        g_CLK_M_PERIOD  : real := 4.36
+    );
+end entity;
+
+architecture tb of tb_freqc is
+
+signal clk   : std_logic;
+signal reset : std_logic;
+signal clk_m : std_logic;
+signal start : std_logic;
+signal ready : std_logic;
+signal freq  : std_logic_vector(g_COUNTER_WIDTH-1 downto 0);
+
+signal end_simulation : boolean := false;
+
+begin
+    cmp_dut: tdc_freqc
+        generic map(
+            g_COUNTER_WIDTH => g_COUNTER_WIDTH,
+            g_TIMER_WIDTH   => g_TIMER_WIDTH
+        )
+        port map(
+            clk_i   => clk,
+            reset_i => reset,
+            clk_m_i => clk_m,
+            start_i => start,
+            ready_o => ready,
+            freq_o  => freq
+        );
+    
+    process
+    begin
+        clk <= '0';
+        wait for g_CLK_PERIOD/2.0 * 1 ns;
+        clk <= '1';
+        wait for g_CLK_PERIOD/2.0 * 1 ns;
+        if end_simulation then
+            wait;
+        end if;
+    end process;
+    
+    process
+    begin
+        clk_m <= '0';
+        wait for g_CLK_M_PERIOD/2.0 * 1 ns;
+        clk_m <= '1';
+        wait for g_CLK_M_PERIOD/2.0 * 1 ns;
+        if end_simulation then
+            wait;
+        end if;
+    end process;
+    
+    process
+    variable v_freq_int       : integer;
+    variable v_ratio_actual   : real;
+    variable v_ratio_measured : real;
+    variable v_error          : real;
+    variable v_max_error      : real;
+    begin
+        start <= '0';
+        reset <= '1';
+        wait until rising_edge(clk);
+        reset <= '0';
+        wait until rising_edge(clk);
+        
+        start <= '1';
+        wait until rising_edge(clk);
+        wait for 1 ns;
+        assert ready = '0' severity failure;
+        start <= '0';
+        wait until ready = '1';
+        v_freq_int := to_integer(unsigned(freq));
+        v_ratio_actual := g_CLK_PERIOD/g_CLK_M_PERIOD;
+        v_ratio_measured := real(v_freq_int)/real(2**g_TIMER_WIDTH-1);
+        v_error := abs(v_ratio_measured-v_ratio_actual);
+        v_max_error := 1.0/real(2**g_TIMER_WIDTH-1);
+        report "Raw measured value: " & integer'image(v_freq_int);
+        report "g_CLK_PERIOD/g_CLK_M_PERIOD (actual): " & real'image(v_ratio_actual);
+        report "g_CLK_PERIOD/g_CLK_M_PERIOD (measured): " & real'image(v_ratio_measured);
+        report "Error: " & real'image(v_error) & " (maximum: " & real'image(v_max_error) & ")";
+        assert v_error <= v_max_error severity failure;
+        
+        report "Test passed.";
+        end_simulation <= true;
+        wait;
+    end process;
+end architecture;