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TDC core
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TDC core
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80ae39d8
Commit
80ae39d8
authored
Oct 24, 2011
by
Sebastien Bourdeauducq
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demo: provide calibration clock
parent
edce0bce
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2 changed files
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18 additions
and
4 deletions
+18
-4
system.v
demo/boards/spec/rtl/system.v
+18
-2
common.ucf
demo/boards/spec/synthesis/common.ucf
+0
-2
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demo/boards/spec/rtl/system.v
View file @
80ae39d8
...
@@ -32,8 +32,7 @@ module system(
...
@@ -32,8 +32,7 @@ module system(
output
[
3
:
0
]
led
,
output
[
3
:
0
]
led
,
// TDC
// TDC
input
[
1
:
0
]
tdc_signal
,
input
[
1
:
0
]
tdc_signal
input
[
1
:
0
]
tdc_calib
)
;
)
;
//------------------------------------------------------------------
//------------------------------------------------------------------
...
@@ -456,6 +455,8 @@ sysctl #(
...
@@ -456,6 +455,8 @@ sysctl #(
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// TDC
// TDC
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
wire
[
1
:
0
]
tdc_calib
;
tdc_hostif
#(
tdc_hostif
#(
.
g_CHANNEL_COUNT
(
2
)
,
.
g_CHANNEL_COUNT
(
2
)
,
.
g_CARRY4_COUNT
(
100
)
,
.
g_CARRY4_COUNT
(
100
)
,
...
@@ -485,4 +486,19 @@ tdc_hostif #(
...
@@ -485,4 +486,19 @@ tdc_hostif #(
.
calib_i
(
tdc_calib
)
.
calib_i
(
tdc_calib
)
)
;
)
;
// startup calibration oscillator
wire
cal_clk16x
;
wire
cal_clk
;
tdc_ringosc
#(
.
g_LENGTH
(
31
)
)
calib_osc
(
.
en_i
(
~
sys_rst
)
,
.
clk_o
(
cal_clk16x
)
)
;
reg
[
3
:
0
]
cal_clkdiv
;
always
@
(
posedge
cal_clk16x
)
cal_clkdiv
<=
cal_clkdiv
+
4'd1
;
assign
cal_clk
=
cal_clkdiv
[
3
]
;
assign
tdc_calib
=
{
2
{
cal_clk
}};
endmodule
endmodule
demo/boards/spec/synthesis/common.ucf
View file @
80ae39d8
...
@@ -26,8 +26,6 @@ NET "led[3]" LOC = C20 | IOSTANDARD = "LVCMOS18";
...
@@ -26,8 +26,6 @@ NET "led[3]" LOC = C20 | IOSTANDARD = "LVCMOS18";
# FIXME
# FIXME
NET "tdc_signal[0]" LOC = AB11 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "tdc_signal[0]" LOC = AB11 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "tdc_signal[1]" LOC = Y11 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "tdc_signal[1]" LOC = Y11 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "tdc_calib[0]" LOC = AB12 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "tdc_calib[1]" LOC = AA12 | IOSTANDARD = LVCMOS25 | PULLDOWN;
# ==== TDC core ====
# ==== TDC core ====
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[0].cmp_channel/muxed_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[0].cmp_channel/muxed_signal" TIG;
...
...
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