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TDC core
Commit 6896864b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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working on the plan B, WIP

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core/Manifest.py deleted 100644 → 0
View file @ c9d9b7d6
files = [
"tdc_controller.vhd", "tdc_freqc.vhd", "tdc_psync.vhd",
"tdc_channelbank.vhd", "tdc_delayline.vhd", "tdc_lbc.vhd", "tdc_ringosc.vhd",
"tdc_channel.vhd", "tdc_divider.vhd", "tdc_package.vhd", "tdc.vhd"
];
core/tdc_channel.vhd deleted 100644 → 0
View file @ c9d9b7d6
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tdc_channel
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Per-channel processing
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-10-25 SB Disable ring oscillator on reset
-- 2011-08-03 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 CERN
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, version 3 of the License.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- DESCRIPTION:
-- This contains the elements needed for each channel:
-- * Delay line
-- * Encoder
-- * LUT
-- * Deskew stage
-- * Online calibration ring oscillator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tdc_package.all;
use work.genram_pkg.all;
entity tdc_channel is
generic(
-- Number of CARRY4 elements.
g_CARRY4_COUNT : positive;
-- Number of raw output bits.
g_RAW_COUNT : positive;
-- Number of fractional part bits.
g_FP_COUNT : positive;
-- Number of coarse counter bits.
g_COARSE_COUNT : positive;
-- Length of the ring oscillator.
g_RO_LENGTH : positive
);
port(
clk_i : in std_logic;
reset_i : in std_logic;
-- Coarse counter and deskew inputs.
coarse_i : in std_logic_vector(g_COARSE_COUNT-1 downto 0);
deskew_i : in std_logic_vector((g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
-- Signal input.
signal_i : in std_logic;
calib_i : in std_logic;
calib_sel_i : in std_logic;
-- Detection outputs.
detect_o : out std_logic;
polarity_o : out std_logic;
raw_o : out std_logic_vector(g_RAW_COUNT-1 downto 0);
fp_o : out std_logic_vector((g_COARSE_COUNT+g_FP_COUNT)-1 downto 0);
-- LUT access.
lut_a_i : in std_logic_vector(g_RAW_COUNT-1 downto 0);
lut_we_i : in std_logic;
lut_d_i : in std_logic_vector(g_FP_COUNT-1 downto 0);
lut_d_o : out std_logic_vector(g_FP_COUNT-1 downto 0);
-- Calibration ring oscillator.
ro_en_i : in std_logic;
ro_clk_o : out std_logic
);
end entity;
architecture rtl of tdc_channel is
signal calib_sel_d : std_logic;
signal muxed_signal : std_logic;
signal inv_signal : std_logic;
signal taps : std_logic_vector(4*g_CARRY4_COUNT-1 downto 0);
signal ipolarity : std_logic;
signal polarity : std_logic;
signal polarity_d1 : std_logic;
signal polarity_d2 : std_logic;
signal detect_d1 : std_logic;
signal raw : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal raw_d1 : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal raw_d2 : std_logic_vector(g_RAW_COUNT-1 downto 0);
signal lut : std_logic_vector(g_FP_COUNT-1 downto 0);
signal ro_en : std_logic;
begin
-- register calibration select signal to avoid glitches
process(clk_i)
begin
if rising_edge(clk_i) then
calib_sel_d <= calib_sel_i;
end if;
end process;
with calib_sel_d select
muxed_signal <= calib_i when '1', signal_i when others;
inv_signal <= muxed_signal xor not ipolarity;
cmp_delayline: tdc_delayline
generic map(
g_WIDTH => g_CARRY4_COUNT
)
port map(
clk_i => clk_i,
reset_i => reset_i,
signal_i => inv_signal,
taps_o => taps
);
cmp_lbc: tdc_lbc
generic map(
g_N => g_RAW_COUNT,
g_NIN => g_CARRY4_COUNT*4,
g_IGNORE => 2
)
port map(
clk_i => clk_i,
reset_i => reset_i,
d_i => taps,
ipolarity_o => ipolarity,
polarity_o => polarity,
count_o => raw
);
cmp_lut: generic_dpram
generic map(
g_data_width => g_FP_COUNT,
g_size => 2**g_RAW_COUNT,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_init_file => "",
g_dual_clock => false
)
port map(
clka_i => clk_i,
clkb_i => '0',
wea_i => '0',
bwea_i => (others => '0'),
aa_i => raw,
da_i => (others => '0'),
qa_o => lut,
web_i => lut_we_i,
bweb_i => (others => '0'),
ab_i => lut_a_i,
db_i => lut_d_i,
qb_o => lut_d_o
);
cmp_ringosc: tdc_ringosc
generic map(
g_LENGTH => g_RO_LENGTH
)
port map(
en_i => ro_en,
clk_o => ro_clk_o
);
ro_en <= ro_en_i and not reset_i;
detect_d1 <= polarity_d1 xor polarity_d2;
process(clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
detect_o <= '0';
polarity_d1 <= '1';
polarity_d2 <= '1';
raw_d1 <= (others => '0');
raw_d2 <= (others => '0');
else
detect_o <= detect_d1;
polarity_d1 <= polarity;
raw_d1 <= raw;
if detect_d1 = '1' then
polarity_d2 <= polarity_d1;
raw_d2 <= raw_d1;
end if;
end if;
end if;
end process;
polarity_o <= polarity_d2;
raw_o <= raw_d2;
-- Combine coarse counter value and deskew.
process(clk_i)
begin
if rising_edge(clk_i) then
if reset_i = '1' then
fp_o <= (others => '0');
else
if detect_d1 = '1' then
fp_o <= std_logic_vector(
unsigned(coarse_i & (lut'range => '0'))
- unsigned(lut)
+ unsigned(deskew_i));
end if;
end if;
end if;
end process;
end architecture;
core/tdc_ordertaps.vhd deleted 100644 → 0
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core/tdc_package.vhd deleted 100644 → 0
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hostif/Manifest.py deleted 100644 → 0
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modules = { "local" : [ "../core" ] }
files = [ "tdc_hostif_package.vhd", "tdc_hostif.vhd", "tdc_wb.vhd" ]
hostif/tdc_hostif.vhd deleted 100644 → 0
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rtl/Manifest.py 0 → 100644
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files = [
"tdc_freqc.vhd",
"tdc_psync.vhd",
"tdc_delayline.vhd",
"tdc_lbc.vhd",
"tdc_ringosc.vhd",
"tdc_channel.vhd",
"tdc_divider.vhd",
"tdc_package.vhd",
"tdc_ordertaps.vhd",
"tdc_order_picker.vhd",
"tdc_channel_wb.vhd",
"tdc_wbgen2_pkg.vhd",
"tdc_core.vhd",
"xwb_urv_mcs.vhd"
];
modules = { "local" : [
"../ip_cores/general-cores",
"../ip_cores/urv-core"] };
rtl/build_wb.sh 0 → 100755
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wbgen2 -H record_full -K ../testbench/include/tdc_channel_wb.vh -V tdc_channel_wb.vhd -p tdc_wbgen2_pkg.vhd tdc_channel_wb.wb
\ No newline at end of file
core/tdc.vhd → rtl/tdc.vhd
View file @ 6896864b
......@@ -127,7 +127,7 @@ signal oc_sfreq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
signal freeze_ack : std_logic;
begin
cmp_channelbank: tdc_channelbank
cmp_channelbank: entity work.tdc_channelbank
generic map(
g_CHANNEL_COUNT => g_CHANNEL_COUNT,
g_CARRY4_COUNT => g_CARRY4_COUNT,
......@@ -178,7 +178,7 @@ begin
oc_sfreq_o => oc_sfreq
);
cmp_controller: tdc_controller
cmp_controller: entity work.tdc_controller
generic map(
g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT,
......
rtl/tdc_channel.vhd 0 → 100644
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rtl/tdc_channel_wb.vhd 0 → 100644
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rtl/tdc_channel_wb.wb 0 → 100644
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-- -*- Mode: LUA; tab-width: 2 -*-
peripheral
{
name = "TDC";
description = "Time to digital converter (signle channel).";
hdl_entity = "tdc_channel_wb";
prefix = "tdc";
reg {
name = "Control and status";
description = "Control and status.";
prefix = "csr";
field {
name = "Reset";
prefix = "rst";
type = MONOSTABLE;
};
field {
name = "Ready";
prefix = "rdy";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TS valid";
prefix = "valid";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Enable ring oscillator";
prefix = "ro_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Calibration control";
prefix = "calr";
field {
name = "Calibration mode select";
prefix = "cal_mode";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Calibration step select";
prefix = "cal_step";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Calibration offset select";
prefix = "cal_offset";
type = SLV;
size = 15;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TS raw CSR";
prefix = "raw_csr";
field {
name = "TS valid";
prefix = "valid";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TS ack";
prefix = "ack";
type = MONOSTABLE;
};
};
reg {
name = "TS raw taps bank select";
prefix = "raw_bank";
field {
name = "raw bank select";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TS raw taps";
prefix = "raw_taps";
field {
name = "raw taps";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "LUT read address";
description = "LUT address to read when debugging.";
prefix = "luta";
field {
name = "Address";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "LUT read data";
description = "LUT data readback for debugging.";
prefix = "lutd";
field {
name = "Data";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Frequency counter current value";
description = "Reports the latest measurement result of the frequency counter for debugging.";
prefix = "fcr";
field {
name = "Result";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Frequency counter stored value";
description = "Reports the latest stored measurement result of the frequency counter for debugging.";
prefix = "fcsr";
field {
name = "Result";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
core/tdc_channelbank.vhd → rtl/tdc_channelbank.vhd
View file @ 6896864b
......@@ -109,7 +109,7 @@ end entity;
architecture rtl of tdc_channelbank is
begin
g_single: if g_CHANNEL_COUNT = 1 generate
cmp_channelbank: tdc_channelbank_single
cmp_channelbank: entity work.tdc_channelbank_single
generic map(
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
......@@ -160,7 +160,7 @@ begin
);
end generate;
g_multi: if g_CHANNEL_COUNT > 1 generate
cmp_channelbank: tdc_channelbank_multi
cmp_channelbank: entity work.tdc_channelbank_multi
generic map(
g_CHANNEL_COUNT => g_CHANNEL_COUNT,
g_CARRY4_COUNT => g_CARRY4_COUNT,
......
core/tdc_channelbank_multi.vhd → rtl/tdc_channelbank_multi.vhd
View file @ 6896864b
......@@ -133,7 +133,7 @@ begin
begin
this_calib_sel <= current_channel_onehot(i) and calib_sel_i;
this_lut_we <= current_channel_onehot(i) and lut_we_i;
cmp_channel: tdc_channel
cmp_channel: entity work.tdc_channel
generic map(
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
......@@ -192,7 +192,7 @@ begin
his_full_a <= current_channel & his_a_i;
-- Frequency counter.
cmp_freqc: tdc_freqc
cmp_freqc: entity work.tdc_freqc
generic map(
g_COUNTER_WIDTH => g_FCOUNTER_WIDTH,
g_TIMER_WIDTH => g_FTIMER_WIDTH
......
core/tdc_channelbank_single.vhd → rtl/tdc_channelbank_single.vhd
View file @ 6896864b
......@@ -105,7 +105,7 @@ signal freq : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
signal sfreq_s : std_logic_vector(g_FCOUNTER_WIDTH-1 downto 0);
begin
-- Per-channel processing.
cmp_channel: tdc_channel
cmp_channel: entity work.tdc_channel
generic map(
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
......@@ -162,7 +162,7 @@ begin
);
-- Frequency counter.
cmp_freqc: tdc_freqc
cmp_freqc: entity work.tdc_freqc
generic map(
g_COUNTER_WIDTH => g_FCOUNTER_WIDTH,
g_TIMER_WIDTH => g_FTIMER_WIDTH
......
core/tdc_controller.vhd → rtl/tdc_controller.vhd
View file @ 6896864b
......@@ -185,7 +185,7 @@ begin
end process;
-- divider
cmp_divider: tdc_divider
cmp_divider: entity work.tdc_divider
generic map(
g_WIDTH => g_FP_COUNT+g_FCOUNTER_WIDTH
)
......
rtl/tdc_core.vhd 0 → 100644
View file @ 6896864b
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity tdc_core is
generic (
g_CARRY4_COUNT : positive := 124;
g_RAW_COUNT : positive := 9;
g_FP_COUNT : positive := 13;
g_COARSE_COUNT : positive := 25;
g_RO_LENGTH : positive := 31);
port (
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_cal_i : in std_logic;
coarse_i : in std_logic_vector(g_COARSE_COUNT-1 downto 0) := (others => '0');
signal_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
dbg_txd_o : out std_logic;
dbg_rxd_i : in std_logic := '1');
end entity tdc_core;
architecture rtl of tdc_core is
constant c_cnx_slave_ports : integer := 2;
constant c_cnx_master_ports : integer := 3;
constant c_master_host : integer := 0;
constant c_master_urv : integer := 1;
constant c_slave_csr : integer := 0;
constant c_slave_vuart : integer := 1;
constant c_slave_tdc : integer := 2;
signal cnx_master_in : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
signal cnx_slave_out : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(c_slave_csr => x"00000000",
c_slave_vuart => x"00001000",
c_slave_tdc => x"00002000"
);
constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
(c_slave_csr => x"0000f000",
c_slave_vuart => x"0000f000",
c_slave_tdc => x"0000f000"
);
begin
slave_o <= cnx_slave_out(c_master_host);
cnx_slave_in(c_master_host) <= slave_i;
U_MCU : entity work.xwb_urv_mcs
generic map (
g_iram_size => 65536,
g_with_host_if => true
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
host_wb_i => cnx_master_out(c_slave_csr),
host_wb_o => cnx_master_in(c_slave_csr),
dwb_o => cnx_slave_in(c_master_urv),
dwb_i => cnx_slave_out(c_master_urv));
U_Host_Intercon : xwb_crossbar
generic map (
g_num_masters => c_cnx_slave_ports,
g_num_slaves => c_cnx_master_ports,
g_registered => true,
g_address => c_cfg_base_addr,
g_mask => c_cfg_base_mask)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
U_CH1 : entity work.tdc_channel
generic map (
g_CARRY4_COUNT => g_CARRY4_COUNT,
g_RAW_COUNT => g_RAW_COUNT,
g_FP_COUNT => g_FP_COUNT,
g_COARSE_COUNT => g_COARSE_COUNT,
g_RO_LENGTH => g_RO_LENGTH)
port map (
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
clk_tdc_i => clk_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
clk_cal_i => clk_cal_i,
coarse_i => coarse_i,
signal_i => signal_i,
slave_i => cnx_master_out(c_slave_tdc),
slave_o => cnx_master_in(c_slave_tdc));
U_VUART : xwb_simple_uart
generic map (
g_with_virtual_uart => true,
g_with_physical_uart => true,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_slave_vuart),
slave_o => cnx_master_in(c_slave_vuart),
uart_rxd_i => dbg_rxd_i,
uart_txd_o => dbg_txd_o);
end rtl;
core/tdc_delayline.vhd → rtl/tdc_delayline.vhd
View file @ 6896864b
......@@ -41,8 +41,8 @@
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
--library unisim;
--use unisim.vcomponents.all;
library work;
use work.tdc_package.all;
......@@ -96,6 +96,7 @@ begin
S => "1111"
);
end generate;
end generate;
-- double latch the output
......@@ -123,11 +124,13 @@ begin
end generate;
-- sort taps by increasing delays, according to static timing model
cmp_ordertaps: tdc_ordertaps
cmp_ordertaps: entity work.tdc_ordertaps
generic map(
g_WIDTH => g_WIDTH
)
port map(
clk_i => clk_i,
rst_i => reset_i,
unsorted_i => taps_rev,
sorted_o => taps_rev_sorted
);
......
core/tdc_freqc.vhd → rtl/tdc_freqc.vhd
View file @ 6896864b
......@@ -92,14 +92,14 @@ begin
end process;
-- Synchronisers.
cmp_sync_start: tdc_psync
cmp_sync_start: entity work.tdc_psync
port map(
clk_src_i => clk_i,
p_i => start,
clk_dst_i => clk_m_i,
p_o => m_start
);
cmp_sync_stop: tdc_psync
cmp_sync_stop: entity work.tdc_psync
port map(
clk_src_i => clk_i,
p_i => stop,
......@@ -107,7 +107,7 @@ begin
p_o => m_stop
);
cmp_sync_stop_ack: tdc_psync
cmp_sync_stop_ack: entity work.tdc_psync
port map(
clk_src_i => clk_m_i,
p_i => m_stop,
......
rtl/tdc_hostif.vhd 0 → 100644
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rtl/tdc_order_picker.vhd 0 → 100644
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tdc_order_picker is
generic(
g_RANGE : integer := 5
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
cfg_i : in std_logic_vector(2*g_RANGE downto 0);
we_i : in std_logic;
unsorted_i : in std_logic_vector(2*g_RANGE downto 0);
picked_o : out std_logic
);
end entity;
architecture rtl of tdc_order_picker is
signal mask : std_logic_vector(2*g_RANGE downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '0' then
mask <= (others => '0');
mask(g_RANGE) <= '1';
elsif we_i = '1' then
mask <= cfg_i;
end if;
end if;
end process;
picked_o <= '0' when unsigned(mask and unsorted_i) = 0 else '1';
end rtl;
rtl/tdc_ordertaps.vhd 0 → 100644
View file @ 6896864b
-- This file was autogenerated by ordertaps.py
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tdc_package.all;
entity tdc_ordertaps is
generic(
g_WIDTH: positive;
g_LUT_ADDR_BITS : positive := 10;
g_RANGE : integer := 2
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
lut_addr_i : in std_logic_vector(g_LUT_ADDR_BITS-1 downto 0) := (others => '0');
lut_data_i : in std_logic_vector(2*g_RANGE downto 0) := (others => '0');
lut_we_i : in std_logic := '0';
unsorted_i : in std_logic_vector(4*g_WIDTH-1 downto 0);
sorted_o : out std_logic_vector(4*g_WIDTH-1 downto 0)
);
end entity;
architecture rtl of tdc_ordertaps is
signal we : std_logic_vector(4*g_WIDTH-1 downto 0);
signal in_vec : std_logic_vector(4*g_WIDTH-1 + 2*g_RANGE+1 downto 0);
begin
process(unsorted_i)
begin
in_vec <= (others => '0');
in_vec( 4*g_WIDTH-1+g_RANGE-1 downto g_RANGE-1 ) <= unsorted_i;
end process;
gen_pickers: for i in 0 to g_WIDTH*4 -1 generate
process(lut_we_i, lut_addr_i) begin
if TO_INTEGER(unsigned(lut_addr_i)) = i then
we(i) <= '1';
else
we(i) <= '0';
end if;
end process;
cmp_picker: entity work.tdc_order_picker
generic map (
g_RANGE => g_RANGE)
port map (
clk_i => clk_i,
rst_i => rst_i,
cfg_i => lut_data_i,
we_i => we(i),
unsorted_i => in_vec(i + 2*g_RANGE downto i),
picked_o => sorted_o(i));
end generate gen_pickers;
end architecture;
rtl/tdc_package.vhd 0 → 100644
View file @ 6896864b
-------------------------------------------------------------------------------
-- TDC Core / CERN
-------------------------------------------------------------------------------
--
-- unit name: tdc_package
--
-- author: Sebastien Bourdeauducq, sebastien@milkymist.org
--
-- description: Component declarations for the TDC core
--
-- references: http://www.ohwr.org/projects/tdc-core
--
-------------------------------------------------------------------------------
-- last changes:
-- 2011-11-07 SB Pre-inversion
-- 2011-11-05 SB Added extra histogram bits support
-- 2011-10-25 SB Added single/multi channel bank components
-- 2011-08-03 SB Created file
-------------------------------------------------------------------------------
-- Copyright (C) 2011 CERN
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, version 3 of the License.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- DESCRIPTION:
-- This contains component declarations for all the modules of the TDC core.
-- It is used both internally to instantiate modules, and by the user to
-- instantiate the top-level "tdc" module.
library ieee;
use ieee.std_logic_1164.all;
package tdc_package is
type t_tdc_timestamp is record
slope : std_logic;
channel : std_logic_vector(2 downto 0);
frac : std_logic_vector(11 downto 0);
coarse : std_logic_vector(31 downto 0);
tai : std_logic_vector(31 downto 0);
seq : std_logic_vector(31 downto 0);
end record;
type t_tdc_timestamp_array is array(integer range<>) of t_tdc_timestamp;
component CARRY4 is
port (
CO : out std_logic_vector(3 downto 0);
O : out std_logic_vector(3 downto 0);
CI : in std_ulogic := 'L';
CYINIT : in std_ulogic := 'L';
DI : in std_logic_vector(3 downto 0);
S : in std_logic_vector(3 downto 0));
end component CARRY4;
component FDR is
generic (
INIT : bit);
port (
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic);
end component FDR;
component LUT2 is
generic (
INIT : bit_vector);
port (
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic);
end component LUT2;
component LUT1 is
generic (
INIT : bit_vector);
port (
O : out std_ulogic;
I0 : in std_ulogic);
end component LUT1;
end package;
core/tdc_ringosc.vhd → rtl/tdc_ringosc.vhd
View file @ 6896864b
......@@ -36,9 +36,6 @@
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.tdc_package.all;
......
hostif/tdc_wb.vhd → rtl/tdc_wb.vhd
View file @ 6896864b
This diff is collapsed.
rtl/tdc_wbgen2_pkg.vhd 0 → 100644
View file @ 6896864b
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC
---------------------------------------------------------------------------------------
-- File : tdc_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from tdc_channel_wb.wb
-- Created : Tue Sep 11 22:15:48 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_channel_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package tdc_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_tdc_in_registers is record
csr_rdy_i : std_logic;
csr_valid_i : std_logic;
raw_csr_valid_i : std_logic;
raw_taps_i : std_logic_vector(31 downto 0);
lutd_i : std_logic_vector(31 downto 0);
fcr_i : std_logic_vector(31 downto 0);
fcsr_i : std_logic_vector(31 downto 0);
end record;
constant c_tdc_in_registers_init_value: t_tdc_in_registers := (
csr_rdy_i => '0',
csr_valid_i => '0',
raw_csr_valid_i => '0',
raw_taps_i => (others => '0'),
lutd_i => (others => '0'),
fcr_i => (others => '0'),
fcsr_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_tdc_out_registers is record
csr_rst_o : std_logic;
csr_ro_en_o : std_logic;
calr_cal_mode_o : std_logic;
calr_cal_step_o : std_logic_vector(14 downto 0);
calr_cal_offset_o : std_logic_vector(14 downto 0);
raw_csr_ack_o : std_logic;
raw_bank_o : std_logic_vector(7 downto 0);
luta_o : std_logic_vector(15 downto 0);
end record;
constant c_tdc_out_registers_init_value: t_tdc_out_registers := (
csr_rst_o => '0',
csr_ro_en_o => '0',
calr_cal_mode_o => '0',
calr_cal_step_o => (others => '0'),
calr_cal_offset_o => (others => '0'),
raw_csr_ack_o => '0',
raw_bank_o => (others => '0'),
luta_o => (others => '0')
);
function "or" (left, right: t_tdc_in_registers) return t_tdc_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component tdc_channel_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tdc_in_registers;
regs_o : out t_tdc_out_registers
);
end component;
end package;
package body tdc_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tdc_in_registers) return t_tdc_in_registers is
variable tmp: t_tdc_in_registers;
begin
tmp.csr_rdy_i := f_x_to_zero(left.csr_rdy_i) or f_x_to_zero(right.csr_rdy_i);
tmp.csr_valid_i := f_x_to_zero(left.csr_valid_i) or f_x_to_zero(right.csr_valid_i);
tmp.raw_csr_valid_i := f_x_to_zero(left.raw_csr_valid_i) or f_x_to_zero(right.raw_csr_valid_i);
tmp.raw_taps_i := f_x_to_zero(left.raw_taps_i) or f_x_to_zero(right.raw_taps_i);
tmp.lutd_i := f_x_to_zero(left.lutd_i) or f_x_to_zero(right.lutd_i);
tmp.fcr_i := f_x_to_zero(left.fcr_i) or f_x_to_zero(right.fcr_i);
tmp.fcsr_i := f_x_to_zero(left.fcsr_i) or f_x_to_zero(right.fcsr_i);
return tmp;
end function;
end package body;
rtl/xwb_urv_mcs.vhd 0 → 100644
View file @ 6896864b
This diff is collapsed.
sw/arch/urv/crt0.S 0 → 100644
View file @ 6896864b
.section .boot, "ax", @progbits
.global _start
_start:
j _entry
.org 0x8
.extern trap_entry
_exception_entry:
j trap_entry
_entry:
la gp, _gp /* Initialize global pointer */
la sp, _fstack
la t0, _fexception_stack
csrrw t0, mscratch, t0
/* clear the bss segment */
la t0, _fbss
la t1, _end
1:
#ifdef __riscv64
sd zero,0(t0)
addi t0, t0, 8
#else
sw zero,0(t0)
addi t0, t0, 4
#endif
bltu t0, t1, 1b
call main
1:
j 1b
sw/arch/urv/emulate.c 0 → 100644
View file @ 6896864b
#include <stdint.h>
struct rv_trap_context {
uint32_t r[32];
uint32_t mstatus;
uint32_t mepc;
uint32_t mbadaddr;
uint32_t mcause;
};
void undefined_insn_handler( struct rv_trap_context *ctx )
{
uint32_t insn = *(volatile uint32_t *)( ctx->mepc );
ctx->r[0] = 0;
uint32_t rs1 = ctx->r[(insn >> 15) & 0x1f];
uint32_t rs2 = ctx->r[(insn >> 20) & 0x1f];
uint32_t rdi = (insn >> 7) & 0x1f;
// we support MUL natively
if ( (insn & 0xfe00707f) == 0x2001033 ) // MULH
ctx->r[rdi] = ( (int64_t)(int32_t)rs1 * (int64_t)(int32_t) rs2) >> 32;
else if ( (insn & 0xfe00707f) == 0x2002033 ) // MULHSU
ctx->r[rdi] = ((int64_t)(int32_t)rs1 * (uint64_t) rs2) >> 32;
else if ( (insn & 0xfe00707f) == 0x2003033 ) // MULHU
ctx->r[rdi] = ((uint64_t) rs1 * (uint64_t) rs2) >> 32;
else if ( (insn & 0xfe00707f) == 0x2004033 ) // DIV
ctx->r[rdi] = (int32_t)rs1 / (int32_t) rs2;
else if ( (insn & 0xfe00707f) == 0x2005033 ) // DIVU
ctx->r[rdi] = (uint32_t)rs1 / (uint32_t) rs2;
else if ( (insn & 0xfe00707f) == 0x2006033 ) // REM
ctx->r[rdi] = (int32_t)rs1 % (int32_t) rs2;
else if ( (insn & 0xfe00707f) == 0x2007033 ) // REMU
ctx->r[rdi] = (uint32_t)rs1 % (uint32_t) rs2;
ctx->mepc += 4;
asm volatile ("csrc mip, 0x4"); // clear exception
}
\ No newline at end of file
sw/arch/urv/irq.S 0 → 100644
View file @ 6896864b
.section .text
.global trap_entry
trap_entry:
csrrw sp,mscratch,sp
addi sp,sp,-320
sw ra,4(sp)
sw gp,12(sp)
sw tp,16(sp)
sw t0,20(sp)
sw t1,24(sp)
sw t2,28(sp)
sw s0,32(sp)
sw s1,36(sp)
sw a0,40(sp)
sw a1,44(sp)
sw a2,48(sp)
sw a3,52(sp)
sw a4,56(sp)
sw a5,60(sp)
sw a6,64(sp)
sw a7,68(sp)
sw s2,72(sp)
sw s3,76(sp)
sw s4,80(sp)
sw s5,84(sp)
sw s6,88(sp)
sw s7,92(sp)
sw s8,96(sp)
sw s9,100(sp)
sw s10,104(sp)
sw s11,108(sp)
sw t3,112(sp)
sw t4,116(sp)
sw t5,120(sp)
sw t6,124(sp)
csrr t0,mscratch
csrr s0,mstatus
csrr t1,mepc
csrr t2,mbadaddr
csrr t3,mcause
sw t0,8(sp)
sw s0,128(sp)
sw t1,132(sp)
sw t2,136(sp)
sw t3,140(sp)
li t0,-1
sw t0,144(sp)
mv a0,sp
la t0, jump_table
sll t3, t3, 2
add t0, t0, t3
lw t0, 0(t0)
la ra, jump_table_return
jr t0
jump_table:
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
.word undefined_handler
jump_table_return:
mv a0,sp
lw t1,128(a0)
lw t2,132(a0)
addi sp,sp,320
csrw mscratch,sp
csrw mepc,t2
lw ra,4(a0)
lw sp,8(a0)
lw gp,12(a0)
lw tp,16(a0)
lw t0,20(a0)
lw t1,24(a0)
lw t2,28(a0)
lw s0,32(a0)
lw s1,36(a0)
lw a1,44(a0)
lw a2,48(a0)
lw a3,52(a0)
lw a4,56(a0)
lw a5,60(a0)
lw a6,64(a0)
lw a7,68(a0)
lw s2,72(a0)
lw s3,76(a0)
lw s4,80(a0)
lw s5,84(a0)
lw s6,88(a0)
lw s7,92(a0)
lw s8,96(a0)
lw s9,100(a0)
lw s10,104(a0)
lw s11,108(a0)
lw t3,112(a0)
lw t4,116(a0)
lw t5,120(a0)
lw t6,124(a0)
lw a0,40(a0)
mret
.weak undefined_handler
undefined_handler:
j undefined_handler
sw/arch/urv/riscv.h 0 → 100644
View file @ 6896864b
#ifndef __RISCV_H
#define __RISCV_H
#ifdef __GNUC__
#define riscv_read_csr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
#define riscv_write_csr(reg, val) \
asm volatile ("csrw " #reg ", %0" :: "r"(val))
#define riscv_swap_csr(reg, val) ({ long __tmp; \
asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
__tmp; })
#define riscv_set_csr(reg, bit) ({ unsigned long __tmp; \
if (__builtin_constant_p(bit) && (bit) < 32) \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; })
#define riscv_clear_csr(reg, bit) ({ unsigned long __tmp; \
if (__builtin_constant_p(bit) && (bit) < 32) \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
else \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
__tmp; })
#define riscv_rdtime() riscv_read_csr(time)
#define riscv_rdcycle() riscv_read_csr(cycle)
#define riscv_rdinstret() riscv_read_csr(instret)
#endif
#endif
sw/arch/urv/urv.ld 0 → 100644
View file @ 6896864b
OUTPUT_FORMAT("elf32-littleriscv")
ENTRY(_start)
MEMORY
{
ram :
ORIGIN = 0x00000000,
LENGTH = 32768 - 2048
stack :
ORIGIN = 32768 - 2048,
LENGTH = 2048
smem :
ORIGIN = 0x40200000,
LENGTH = 65536
}
SECTIONS
{
/*--------------------------------------------------------------------*/
/* Code and read-only segment */
/*--------------------------------------------------------------------*/
/* Begining of code and text segment */
. = 0x00000000;
_ftext = .;
PROVIDE( eprol = . );
/* text: Program code section */
.text :
{
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
} > ram
/* init: Code to execute before main (called by crt0.S) */
.init :
{
KEEP( *(.init) )
} > ram
/* fini: Code to execute after main (called by crt0.S) */
.fini :
{
KEEP( *(.fini) )
} > ram
/* rodata: Read-only data */
.rodata :
{
*(.rdata)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
} > ram
/* End of code and read-only segment */
PROVIDE( etext = . );
_etext = .;
/*--------------------------------------------------------------------*/
/* Global constructor/destructor segement */
/*--------------------------------------------------------------------*/
/* The .ctors/.dtors sections are special sections which contain a
list of constructor/destructor function pointers. crtbegin.o
includes code in a .init section which goes through the .ctors list
and calls each constuctor. crtend.o includes code in a .fini
section which goes through the .dtors list and calls each
destructor. crtbegin.o includes a special null pointer in its own
.ctors/.dtors sections which acts as a start indicator for those
lists. crtend.o also includes a special null pointer in its own
.ctors/.dtors sections which acts as an end indictor. The linker
commands below are setup so that crtbegin.o's .ctors/.dtors
sections are always first and crtend.o's .ctors/.dtors sections are
always last. This is the only way the list of functions will have
the begin and end indicators in the right place. */
/* ctors : Array of global constructor function pointers */
/*--------------------------------------------------------------------*/
/* Initialized data segment */
/*--------------------------------------------------------------------*/
/* Start of initialized data segment */
. = ALIGN(16);
_fdata = .;
/* data: Writable data */
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
} > ram
/* End of initialized data segment */
PROVIDE( edata = . );
_edata = .;
/* Have _gp point to middle of sdata/sbss to maximize displacement range */
. = ALIGN(16);
_gp = . + 0x800;
/* Writable small data segment */
.sdata :
{
*(.sdata)
*(.sdata.*)
*(.srodata.*)
*(.gnu.linkonce.s.*)
} > ram
/*--------------------------------------------------------------------*/
/* Uninitialized data segment */
/*--------------------------------------------------------------------*/
/* Start of uninitialized data segment */
. = ALIGN(8);
_fbss = .;
/* Writable uninitialized small data segment */
.sbss :
{
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
} > ram
/* bss: Uninitialized writeable data section */
. = .;
_bss_start = .;
.bss :
{
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
} > ram
/* End of uninitialized data segment (used by syscalls.c for heap) */
PROVIDE( end = . );
_end = ALIGN(8);
.smem : { *(.smem) } > smem
PROVIDE(_endram = ORIGIN(stack));
PROVIDE(_fexception_stack = ORIGIN(stack) + LENGTH(stack) - 4);
PROVIDE(_fstack = ORIGIN(stack) + LENGTH(stack) - 4 - 0x400 );
}
sw/arch/urv/urv.mk 0 → 100644
View file @ 6896864b
# and don't touch the rest unless you know what you're doing.
CROSS_COMPILE ?= riscv32-elf-
CC = $(CROSS_COMPILE)gcc
LD = $(CROSS_COMPILE)ld
OBJDUMP = $(CROSS_COMPILE)objdump
OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
CFLAGS = -g -O2 -I. -I../common -I../../include -I../include/ -mabi=ilp32 -march=rv32im -ffunction-sections -fdata-sections
OBJS += ../arch/urv/crt0.o ../arch/urv/irq.o ../arch/urv/emulate.o ../common/printf.o ../common/vsprintf-xint.o ../common/board.o ../common/uart.o
LDSCRIPT = ../arch/urv/urv.ld
LDFLAGS = -Wl,--gc-sections
$(OUTPUT): $(LDSCRIPT) $(OBJS)
${CC} ${CFLAGS} ${LDFLAGS} -g -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc
${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -S $(OUTPUT).elf > disasm.S
# ../common/genraminit $(OUTPUT).bin > $(OUTPUT).ram
$(SIZE) $(OUTPUT).elf
../arch/urv/emulate.o: ../arch/urv/emulate.c
${CC} -O2 -mabi=ilp32 -march=rv32i -c $^ -o $@ -I.
%.o: %.S
${CC} -mabi=ilp32 -march=rv32i -c $^ -o $@
clean:
rm -f $(OBJS) $(OUTPUT).bin
\ No newline at end of file
sw/common/board.c 0 → 100644
View file @ 6896864b
#include "board.h"
#include "uart.h"
void board_init()
{
uart_init_hw();
}
\ No newline at end of file
sw/common/board.h 0 → 100644
View file @ 6896864b
#ifndef __BOARD_H
#define __BOARD_H
#include <stdint.h>
#define SYSTEM_CLOCK_FREQ 62500000
#define UART_BAUDRATE (SYSTEM_CLOCK_FREQ/2)
#define BASE_UART (void *) 0x00081000
static inline uint32_t board_system_freq()
{
return SYSTEM_CLOCK_FREQ;
}
static inline void usleep(int us)
{
int t = us * board_system_freq() / 5000000;
while(t--) asm volatile("nop");
}
static inline uint32_t readl(uint32_t addr)
{
return *(volatile uint32_t *)(addr);
}
static inline void writel(uint32_t data, uint32_t addr)
{
*(volatile uint32_t *)(addr) = data;
}
#endif
sw/common/gpio.c 0 → 100644
View file @ 6896864b
#include "board.h"
#include "gpio.h"
#define GPIO_REG_COR 0
#define GPIO_REG_SOR 4
#define GPIO_REG_DDR 8
#define GPIO_REG_PSR 12
#define GPIO_BANK_SIZE 32
static void wb_gpio_set_dir(const struct gpio_pin *pin, int dir)
{
void *base = (void*)pin->rwops->priv;
volatile uint32_t *dr = base + (GPIO_BANK_SIZE * (pin->pin >> 5)) + GPIO_REG_DDR;
uint32_t mask = 1 << (pin->pin & 0x1f);
if (dir)
*dr |= mask;
else
*dr &= ~mask;
}
static void wb_gpio_out(const struct gpio_pin *pin, int value)
{
void *base = (void*)pin->rwops->priv;
volatile void *regs = base + (GPIO_BANK_SIZE * (pin->pin >> 5));
uint32_t mask = 1 << (pin->pin & 0x1f);
if(value)
*(volatile uint32_t *)(regs + GPIO_REG_SOR) = mask;
else
*(volatile uint32_t *)(regs + GPIO_REG_COR) = mask;
}
static int wb_gpio_in(const struct gpio_pin *pin)
{
void *base = (void*)pin->rwops->priv;
volatile uint32_t *psr = base + (GPIO_BANK_SIZE * (pin->pin >> 5)) + GPIO_REG_PSR;
uint32_t mask = 1 << (pin->pin & 0x1f);
return (*psr & mask) ? 1 : 0;
}
struct gpio_rwops gpio_main = {
BASE_GPIO,
wb_gpio_set_dir,
wb_gpio_out,
wb_gpio_in
};
sw/common/gpio.h 0 → 100644
View file @ 6896864b
#ifndef __GPIO_H
#define __GPIO_H
#include "board.h"
struct gpio_pin;
typedef void (*set_dir_func)(const struct gpio_pin *, int);
typedef void (*set_out_func)(const struct gpio_pin *, int);
typedef int (*read_pin_func)(const struct gpio_pin *);
struct gpio_rwops
{
void* priv;
set_dir_func set_dir;
set_out_func set_out;
read_pin_func read_pin;
};
struct gpio_pin
{
const struct gpio_rwops *rwops;
int pin;
};
extern struct gpio_rwops gpio_main;
extern struct gpio_rwops gpio_rtm;
static inline void gpio_set_dir(const struct gpio_pin *pin, int dir)
{
pin->rwops->set_dir(pin, dir);
}
static inline void gpio_out(const struct gpio_pin *pin, int value)
{
pin->rwops->set_out(pin, value);
}
static inline int gpio_in(const struct gpio_pin *pin)
{
return pin->rwops->read_pin(pin);
}
static const struct gpio_pin gpio_pin_clk_muxab_sel0 = { &gpio_main, 23 };
static const struct gpio_pin gpio_pin_clk_muxab_sel1 = { &gpio_main, 24 };
static const struct gpio_pin gpio_pin_clk_mux1a_sel0 = { &gpio_main, 25 };
static const struct gpio_pin gpio_pin_clk_mux1a_sel1 = { &gpio_main, 26 };
static const struct gpio_pin gpio_pin_clk_mux1b_sel0 = { &gpio_main, 27 };
static const struct gpio_pin gpio_pin_clk_mux1b_sel1 = { &gpio_main, 28 };
static const struct gpio_pin gpio_pin_clk_mux2a_sel0 = { &gpio_main, 29 };
static const struct gpio_pin gpio_pin_clk_mux2a_sel1 = { &gpio_main, 30 };
static const struct gpio_pin gpio_pin_clk_mux2b_sel0 = { &gpio_main, 32 };
static const struct gpio_pin gpio_pin_clk_mux2b_sel1 = { &gpio_main, 33 };
static const struct gpio_pin gpio_pin_clk_mux_dac_sel0 = { &gpio_main, 57 };
static const struct gpio_pin gpio_pin_clk_mux_dac_sel1 = { &gpio_main, 58 };
static const struct gpio_pin gpio_pin_si_rst_n = { &gpio_main, 16 };
static const struct gpio_pin gpio_pin_si_spi_sclk = { &gpio_main, 20 };
static const struct gpio_pin gpio_pin_si_spi_di = { &gpio_main, 21 };
static const struct gpio_pin gpio_pin_si_spi_do = { &gpio_main, 22 }; // Si3
static const struct gpio_pin gpio_pin_si_spi_cs_n1 = { &gpio_main, 19 };
static const struct gpio_pin gpio_pin_div_spi_sclk = { &gpio_main, 34 };
static const struct gpio_pin gpio_pin_div_spi_dio = { &gpio_main, 35 };
static const struct gpio_pin gpio_pin_div_spi_cs_n1 = { &gpio_main, 36 };
static const struct gpio_pin gpio_pin_div_spi_cs_n2 = { &gpio_main, 37 };
static const struct gpio_pin gpio_pin_div_function = { &gpio_main, 40 };
static const struct gpio_pin gpio_pin_adc_sync = { &gpio_main, 41};
static const struct gpio_pin gpio_pin_adc_oeb_l = { &gpio_main, 42};
static const struct gpio_pin gpio_pin_adc_pwdn = { &gpio_main, 43};
static const struct gpio_pin gpio_pin_adc_spi_cs_l1 = { &gpio_main, 45 };
static const struct gpio_pin gpio_pin_adc_spi_cs_l2 = { &gpio_main, 46 };
static const struct gpio_pin gpio_pin_adc_spi_cs_l3 = { &gpio_main, 47 };
static const struct gpio_pin gpio_pin_adc_spi_cs_l4 = { &gpio_main, 48 };
static const struct gpio_pin gpio_pin_adc_spi_cs_l5 = { &gpio_main, 49 };
static const struct gpio_pin gpio_pin_adc_spi_sclk = { &gpio_main, 50 };
static const struct gpio_pin gpio_pin_adc_spi_dio = { &gpio_main, 51 };
static const struct gpio_pin gpio_pin_rtm_usr_scl = { &gpio_main, 55 };
static const struct gpio_pin gpio_pin_rtm_usr_sda = { &gpio_main, 56 };
static const struct gpio_pin gpio_pin_leds[] =
{
{ &gpio_main, 0 },
{ &gpio_main, 1 },
{ &gpio_main, 2 },
{ &gpio_main, 3 },
{ &gpio_main, 4 },
{ &gpio_main, 5 },
{ &gpio_main, 6 },
{ &gpio_main, 7 },
{ &gpio_main, 8 },
{ &gpio_main, 9 },
{ &gpio_main, 10 },
{ &gpio_main, 11 },
{ &gpio_main, 12 },
{ &gpio_main, 13 },
{ &gpio_main, 14 },
{ &gpio_main, 15 }
};
#endif
sw/common/hw/wb_uart.h 0 → 100644
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/*
Register definitions for slave core: Simple Wishbone UART
* File : ../../../../software/include/hw/wb_uart.h
* Author : auto-generated by wbgen2 from uart.wb
* Created : Mon Feb 21 22:25:02 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_UART_WB
#define __WBGEN2_REGDEFS_UART_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status Register */
/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Baudrate control register */
/* definitions for register: Transmit data regsiter */
/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT 0
#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: Receive data regsiter */
/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT 0
#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Status Register */
#define UART_REG_SR 0x00000000
/* [0x4]: REG Baudrate control register */
#define UART_REG_BCR 0x00000004
/* [0x8]: REG Transmit data regsiter */
#define UART_REG_TDR 0x00000008
/* [0xc]: REG Receive data regsiter */
#define UART_REG_RDR 0x0000000c
PACKED struct UART_WB {
/* [0x0]: REG Status Register */
uint32_t SR;
/* [0x4]: REG Baudrate control register */
uint32_t BCR;
/* [0x8]: REG Transmit data regsiter */
uint32_t TDR;
/* [0xc]: REG Receive data regsiter */
uint32_t RDR;
};
#endif
sw/common/pp-printf.h 0 → 100644
View file @ 6896864b
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Alessandro Rubini <rubini@gnudd.com>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#ifndef __PP_PRINTF_H
#define __PP_PRINTF_H
#include <stdarg.h>
#define CONFIG_PRINT_BUFSIZE 128
extern int pp_printf(const char *fmt, ...)
__attribute__((format(printf,1,2)));
extern int pp_sprintf(char *s, const char *fmt, ...)
__attribute__((format(printf,2,3)));
extern int pp_vprintf(const char *fmt, va_list args);
extern int pp_vsprintf(char *buf, const char *, va_list)
__attribute__ ((format (printf, 2, 0)));
/* This is what we rely on for output */
extern int puts(const char *s);
#endif
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-include Makefile.specific
CROSS_COMPILE ?= riscv32-elf-
CPU = urv
OBJS = main.o
OUTPUT = test
include ../arch/urv/urv.mk
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