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TDC core
Commit 5c8ecef1 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
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controller: work around GHDL bug

parent 169643f9
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Showing with 3 additions and 4 deletions
core/tdc_controller.vhd
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...@@ -85,6 +85,7 @@ signal mul_d1 : std_logic_vector(g_FP_COUNT+g_FCOUNTER_WIDTH-1 downto 0); ...@@ -85,6 +85,7 @@ signal mul_d1 : std_logic_vector(g_FP_COUNT+g_FCOUNTER_WIDTH-1 downto 0);
signal div_start : std_logic; signal div_start : std_logic;
signal div_ready : std_logic; signal div_ready : std_logic;
signal div_divisor : std_logic_vector(g_FP_COUNT+g_FCOUNTER_WIDTH-1 downto 0);
signal div_quotient : std_logic_vector(g_FP_COUNT+g_FCOUNTER_WIDTH-1 downto 0); signal div_quotient : std_logic_vector(g_FP_COUNT+g_FCOUNTER_WIDTH-1 downto 0);
signal div_qsat : std_logic_vector(g_FP_COUNT-1 downto 0); signal div_qsat : std_logic_vector(g_FP_COUNT-1 downto 0);
...@@ -174,15 +175,13 @@ begin ...@@ -174,15 +175,13 @@ begin
start_i => div_start, start_i => div_start,
dividend_i => mul_d1, dividend_i => mul_d1,
divisor_i(g_FP_COUNT+g_FCOUNTER_WIDTH-1 downto g_FCOUNTER_WIDTH) divisor_i => div_divisor,
=> (others => '0'),
divisor_i(g_FCOUNTER_WIDTH-1 downto 0)
=> oc_freq_i,
ready_o => div_ready, ready_o => div_ready,
quotient_o => div_quotient, quotient_o => div_quotient,
remainder_o => open remainder_o => open
); );
div_divisor <= (g_FP_COUNT-1 downto 0 => '0') & oc_freq_i;
process(div_quotient) process(div_quotient)
begin begin
if div_quotient(g_FP_COUNT+g_FCOUNTER_WIDTH-1 downto g_FP_COUNT) if div_quotient(g_FP_COUNT+g_FCOUNTER_WIDTH-1 downto g_FP_COUNT)
......
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