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TDC core
Commit 3fb9966d authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
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LBC: Test pipelining and polarity inversion

parent 2306f7f5
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Showing with 54 additions and 37 deletions
core/tdc_lbc.vhd
View file @ 3fb9966d
...@@ -78,11 +78,11 @@ begin ...@@ -78,11 +78,11 @@ begin
end function; end function;
signal polarity : std_logic; signal polarity : std_logic;
signal polarity_d1 : std_logic;
signal polarity_d2 : std_logic;
signal count_reg : std_logic_vector(g_N-1 downto 0); signal count_reg : std_logic_vector(g_N-1 downto 0);
signal d_completed : std_logic_vector(2**g_N-2 downto 0); signal d_completed : std_logic_vector(2**g_N-2 downto 0);
begin begin
polarity_o <= polarity;
g_expand: if g_NIN < 2**g_N-1 generate g_expand: if g_NIN < 2**g_N-1 generate
d_completed <= d_i & (2**g_N-1-g_NIN-1 downto 0 => not polarity); d_completed <= d_i & (2**g_N-1-g_NIN-1 downto 0 => not polarity);
end generate; end generate;
...@@ -95,13 +95,18 @@ begin ...@@ -95,13 +95,18 @@ begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if reset_i = '1' then if reset_i = '1' then
polarity <= '1'; polarity <= '1';
polarity_d1 <= '1';
polarity_d2 <= '1';
count_reg <= (others => '0'); count_reg <= (others => '0');
count_o <= (others => '0'); count_o <= (others => '0');
else else
polarity <= not d_completed(2**g_N-2); polarity <= not d_completed(2**g_N-2);
polarity_d1 <= polarity;
polarity_d2 <= polarity_d1;
count_reg <= f_cls(d_completed, polarity); count_reg <= f_cls(d_completed, polarity);
count_o <= count_reg; count_o <= count_reg;
end if; end if;
end if; end if;
end process; end process;
polarity_o <= polarity_d2;
end architecture; end architecture;
tb/lbc/tb_lbc.vhd
View file @ 3fb9966d
...@@ -12,13 +12,12 @@ ...@@ -12,13 +12,12 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- last changes: -- last changes:
-- 2011-08-12 SB Test pipelining and polarity inversion
-- 2011-08-03 SB Created file -- 2011-08-03 SB Created file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Copyright (C) 2011 Sebastien Bourdeauducq -- Copyright (C) 2011 Sebastien Bourdeauducq
-- TODO: test pipelining and polarity inversion
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
...@@ -67,7 +66,6 @@ end function; ...@@ -67,7 +66,6 @@ end function;
signal clk : std_logic; signal clk : std_logic;
signal reset : std_logic; signal reset : std_logic;
signal d : std_logic_vector(2**g_N-2 downto 0); signal d : std_logic_vector(2**g_N-2 downto 0);
signal d_bak : std_logic_vector(2**g_N-2 downto 0);
signal count : std_logic_vector(g_N-1 downto 0); signal count : std_logic_vector(g_N-1 downto 0);
signal polarity : std_logic; signal polarity : std_logic;
...@@ -78,54 +76,68 @@ begin ...@@ -78,54 +76,68 @@ begin
g_NIN => 2**g_N-1 g_NIN => 2**g_N-1
) )
port map( port map(
clk_i => clk, clk_i => clk,
reset_i => reset, reset_i => reset,
d_i => d, d_i => d,
count_o => count, count_o => count,
polarity_o => polarity polarity_o => polarity
); );
reset <= '0';
process process
variable v_polarity : std_logic;
variable v_d : std_logic_vector(2**g_N-2 downto 0);
variable v_seed1 : positive := 1; variable v_seed1 : positive := 1;
variable v_seed2 : positive := 2; variable v_seed2 : positive := 2;
variable v_rand : real; variable v_rand : real;
variable v_int_rand : integer; variable v_int_rand : integer;
variable v_stim : std_logic_vector(0 downto 0); variable v_stim : std_logic_vector(0 downto 0);
begin begin
-- reset -- reset
reset <= '1'; reset <= '1';
clk <= '0'; clk <= '0';
wait for 4 ns; wait for 5 ns;
clk <= '1'; clk <= '1';
wait for 4 ns; wait for 5 ns;
reset <= '0'; reset <= '0';
for i in 0 to 2**g_N-1 loop for i in 1 to 2**g_N+2-1 loop
-- generate test vector -- generate test vector
for j in 0 to 2**g_N-2 loop if i < 2**g_N then
if j > 2**g_N-2-i then if i rem 2 = 0 then
d(j) <= '1'; v_polarity := '0';
elsif j = 2**g_N-2-i then else
d(j) <= '0'; v_polarity := '1';
end if;
for j in 0 to 2**g_N-2 loop
if j > 2**g_N-2-i then
v_d(j) := v_polarity;
elsif j = 2**g_N-2-i then
v_d(j) := not v_polarity;
else
uniform(v_seed1, v_seed2, v_rand);
v_int_rand := integer(trunc(v_rand*2.0));
v_stim := std_logic_vector(to_unsigned(v_int_rand, v_stim'length));
v_d(j) := v_stim(0);
end if;
end loop;
report "Vector out: " & str(v_d) & " (polarity: " & chr(v_polarity) & ")";
d <= v_d;
end if;
-- verify output
if i > 2 then
if i rem 2 = 0 then
v_polarity := '0';
else else
uniform(v_seed1, v_seed2, v_rand); v_polarity := '1';
v_int_rand := integer(trunc(v_rand*2.0));
v_stim := std_logic_vector(to_unsigned(v_int_rand, v_stim'length));
d(j) <= v_stim(0);
end if; end if;
end loop; report "Result in: expected:" & integer'image(i-2) & "(" & chr(v_polarity) & ") output:" & integer'image(to_integer(unsigned(count))) & "(" & chr(polarity) & ")";
wait for 0 ns; assert v_polarity = polarity severity failure;
d_bak <= d; assert i-2 = to_integer(unsigned(count)) severity failure;
-- generate, print and verify output end if;
for j in 0 to 1 loop -- pulse clock
clk <= '0'; clk <= '0';
wait for 4 ns; wait for 5 ns;
clk <= '1'; clk <= '1';
wait for 4 ns; wait for 5 ns;
d <= (others => '0');
end loop;
report "Vector:" & str(d_bak) & " Expected:" & integer'image(i) & " Result:" & integer'image(to_integer(unsigned(count))) & "(" & chr(polarity) & ")";
assert i = to_integer(unsigned(count)) severity failure;
end loop; end loop;
report "Test passed."; report "Test passed.";
wait; wait;
......
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