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TDC core
Commit 3d934c48 authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
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Prefix variables with v

parent 6af2b4a1
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Showing with 20 additions and 20 deletions
tb/lbc/tb_lbc.vhd
View file @ 3d934c48
...@@ -31,20 +31,20 @@ end entity; ...@@ -31,20 +31,20 @@ end entity;
architecture tb of tb_lbc is architecture tb of tb_lbc is
function chr(sl: std_logic) return character is function chr(sl: std_logic) return character is
variable c: character; variable v_c: character;
begin begin
case sl is case sl is
when 'U' => c:= 'U'; when 'U' => v_c:= 'U';
when 'X' => c:= 'X'; when 'X' => v_c:= 'X';
when '0' => c:= '0'; when '0' => v_c:= '0';
when '1' => c:= '1'; when '1' => v_c:= '1';
when 'Z' => c:= 'Z'; when 'Z' => v_c:= 'Z';
when 'W' => c:= 'W'; when 'W' => v_c:= 'W';
when 'L' => c:= 'L'; when 'L' => v_c:= 'L';
when 'H' => c:= 'H'; when 'H' => v_c:= 'H';
when '-' => c:= '-'; when '-' => v_c:= '-';
end case; end case;
return c; return v_c;
end function; end function;
function str(slv: std_logic_vector) return string is function str(slv: std_logic_vector) return string is
...@@ -75,11 +75,11 @@ begin ...@@ -75,11 +75,11 @@ begin
); );
polarity <= '0'; polarity <= '0';
process process
variable seed1 : positive := 1; variable v_seed1 : positive := 1;
variable seed2 : positive := 2; variable v_seed2 : positive := 2;
variable rand : real; variable v_rand : real;
variable int_rand : integer; variable v_int_rand : integer;
variable stim : std_logic_vector(0 downto 0); variable v_stim : std_logic_vector(0 downto 0);
begin begin
for i in 0 to 2**g_N-1 loop for i in 0 to 2**g_N-1 loop
-- generate test vector -- generate test vector
...@@ -89,10 +89,10 @@ begin ...@@ -89,10 +89,10 @@ begin
elsif j = 2**g_N-2-i then elsif j = 2**g_N-2-i then
d(j) <= '0'; d(j) <= '0';
else else
uniform(seed1, seed2, rand); uniform(v_seed1, v_seed2, v_rand);
int_rand := integer(trunc(rand*2.0)); v_int_rand := integer(trunc(v_rand*2.0));
stim := std_logic_vector(to_unsigned(int_rand, stim'length)); v_stim := std_logic_vector(to_unsigned(v_int_rand, v_stim'length));
d(j) <= stim(0); d(j) <= v_stim(0);
end if; end if;
end loop; end loop;
-- generate, print and verify output -- generate, print and verify output
......
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