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TDC core
Commit 3837445d authored by Sebastien Bourdeauducq's avatar Sebastien Bourdeauducq
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demo: adapt to the SPEC board

parent 60aaf965
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Showing with 43 additions and 9 deletions
demo/boards/spec/rtl/system.v
View file @ 3837445d
...@@ -19,16 +19,17 @@ ...@@ -19,16 +19,17 @@
`include "setup.v" `include "setup.v"
module system( module system(
input clkin, input clkin_p,
input resetin, input clkin_n,
input resetin_n,
// UART // UART
input uart_rxd, input uart_rxd,
output uart_txd, output uart_txd,
// GPIO // GPIO
input [2:0] btn, input btn,
output [1:0] led, output [3:0] led,
// TDC // TDC
input [1:0] tdc_signal, input [1:0] tdc_signal,
...@@ -39,9 +40,14 @@ module system( ...@@ -39,9 +40,14 @@ module system(
// Clock and Reset Generation // Clock and Reset Generation
//------------------------------------------------------------------ //------------------------------------------------------------------
wire sys_clk; wire sys_clk;
wire resetin = ~resetin_n;
wire hard_reset; wire hard_reset;
assign sys_clk = clkin; IBUFGDS clkbuf(
.I(clkin_p),
.IB(clkin_n),
.O(sys_clk)
);
`ifndef SIMULATION `ifndef SIMULATION
/* Synchronize the reset input */ /* Synchronize the reset input */
...@@ -425,8 +431,8 @@ uart #( ...@@ -425,8 +431,8 @@ uart #(
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
sysctl #( sysctl #(
.csr_addr(4'h1), .csr_addr(4'h1),
.ninputs(3), .ninputs(1),
.noutputs(2), .noutputs(4),
.systemid(32'h53504543) /* SPEC */ .systemid(32'h53504543) /* SPEC */
) sysctl ( ) sysctl (
.sys_clk(sys_clk), .sys_clk(sys_clk),
......
demo/boards/spec/synthesis/common.ucf
View file @ 3837445d
# ==== Clock input ==== # ==== Clock input ====
NET "clkin" TNM_NET = CLK_125MHZ; NET "sys_clk" TNM_NET = CLK_125MHZ;
TIMESPEC TS_CLK_125MHZ = PERIOD CLK_125MHZ 8 ns; TIMESPEC TS_CLK_125MHZ = PERIOD CLK_125MHZ 8 ns;
# FPGA_CLK from CDCM61004, 125MHz
NET "clkin_p" LOC = G9 | IOSTANDARD = "LVDS_25";
NET "clkin_n" LOC = F10 | IOSTANDARD = "LVDS_25";
# AUX button 0
NET "resetin_n" LOC = C22 | IOSTANDARD = "LVCMOS18";
# ==== UART ====
NET "uart_rxd" LOC = A2 | IOSTANDARD = "LVCMOS25"; # FPGA input
NET "uart_txd" LOC = B2 | IOSTANDARD = "LVCMOS25"; # FPGA output
# ==== GPIO ====
NET "btn" LOC = D21 | IOSTANDARD = "LVCMOS18"; # AUX button 1
NET "led[0]" LOC = G19 | IOSTANDARD = "LVCMOS18"; # AUX LEDs
NET "led[1]" LOC = F20 | IOSTANDARD = "LVCMOS18";
NET "led[2]" LOC = F18 | IOSTANDARD = "LVCMOS18";
NET "led[3]" LOC = C20 | IOSTANDARD = "LVCMOS18";
# TODO: temperature probe
# ==== TDC inputs ====
# FIXME
NET "tdc_signal[0]" LOC = AB11 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "tdc_signal[1]" LOC = Y11 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "tdc_calib[0]" LOC = AB12 | IOSTANDARD = LVCMOS25 | PULLDOWN;
NET "tdc_calib[1]" LOC = AA12 | IOSTANDARD = LVCMOS25 | PULLDOWN;
# ==== TDC core ====
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[0].cmp_channel/muxed_signal" TIG; NET "tdc/cmp_tdc/cmp_channelbank/g_channels[0].cmp_channel/muxed_signal" TIG;
NET "tdc/cmp_tdc/cmp_channelbank/g_channels[1].cmp_channel/muxed_signal" TIG; NET "tdc/cmp_tdc/cmp_channelbank/g_channels[1].cmp_channel/muxed_signal" TIG;
demo/boards/spec/synthesis/system.xst
View file @ 3837445d
...@@ -5,4 +5,4 @@ run ...@@ -5,4 +5,4 @@ run
-opt_mode SPEED -opt_mode SPEED
-opt_level 2 -opt_level 2
-ofn system.ngc -ofn system.ngc
-p xc6slx45t-fgg484-2 -p xc6slx45t-fgg484-3
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