tdc_wb.vhd 48.4 KB
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-- Title          : Wishbone slave core for TDC
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-- File           : tdc_wb.vhd
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-- Author         : auto-generated by wbgen2 from tdc.wb
-- Created        : Tue Oct 25 16:54:19 2011
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-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc.wb
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-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;

entity tdc_wb is
  port (
    rst_n_i                                  : in     std_logic;
    wb_clk_i                                 : in     std_logic;
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    wb_addr_i                                : in     std_logic_vector(5 downto 0);
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    wb_data_i                                : in     std_logic_vector(31 downto 0);
    wb_data_o                                : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_irq_o                                 : out    std_logic;
-- Port for MONOSTABLE field: 'Reset' in reg: 'Control and status'
    tdc_cs_rst_o                             : out    std_logic;
-- Port for BIT field: 'Ready' in reg: 'Control and status'
    tdc_cs_rdy_i                             : in     std_logic;
-- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 0 (high word)'
    tdc_desh0_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 0 (low word)'
    tdc_desl0_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 1 (high word)'
    tdc_desh1_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 1 (low word)'
    tdc_desl1_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 2 (high word)'
    tdc_desh2_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 2 (low word)'
    tdc_desl2_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 3 (high word)'
    tdc_desh3_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 3 (low word)'
    tdc_desl3_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 4 (high word)'
    tdc_desh4_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 4 (low word)'
    tdc_desl4_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 5 (high word)'
    tdc_desh5_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 5 (low word)'
    tdc_desl5_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 6 (high word)'
    tdc_desh6_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 6 (low word)'
    tdc_desl6_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 7 (high word)'
    tdc_desh7_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 7 (low word)'
    tdc_desl7_o                              : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Detected polarities'
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    tdc_pol_i                                : in     std_logic_vector(7 downto 0);
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-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 0'
    tdc_raw0_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 0 (high word)'
    tdc_mesh0_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 0 (low word)'
    tdc_mesl0_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 1'
    tdc_raw1_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 1 (high word)'
    tdc_mesh1_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 1 (low word)'
    tdc_mesl1_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 2'
    tdc_raw2_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 2 (high word)'
    tdc_mesh2_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 2 (low word)'
    tdc_mesl2_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 3'
    tdc_raw3_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 3 (high word)'
    tdc_mesh3_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 3 (low word)'
    tdc_mesl3_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 4'
    tdc_raw4_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 4 (high word)'
    tdc_mesh4_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 4 (low word)'
    tdc_mesl4_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 5'
    tdc_raw5_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 5 (high word)'
    tdc_mesh5_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 5 (low word)'
    tdc_mesl5_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 6'
    tdc_raw6_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 6 (high word)'
    tdc_mesh6_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 6 (low word)'
    tdc_mesl6_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 7'
    tdc_raw7_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 7 (high word)'
    tdc_mesh7_i                              : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 7 (low word)'
    tdc_mesl7_i                              : in     std_logic_vector(31 downto 0);
    irq_ie0_i                                : in     std_logic;
    irq_ie1_i                                : in     std_logic;
    irq_ie2_i                                : in     std_logic;
    irq_ie3_i                                : in     std_logic;
    irq_ie4_i                                : in     std_logic;
    irq_ie5_i                                : in     std_logic;
    irq_ie6_i                                : in     std_logic;
    irq_ie7_i                                : in     std_logic;
    irq_isc_i                                : in     std_logic;
    irq_icc_i                                : in     std_logic;
-- Port for BIT field: 'Freeze request' in reg: 'Debug control'
    tdc_dctl_req_o                           : out    std_logic;
-- Port for BIT field: 'Freeze acknowledgement' in reg: 'Debug control'
    tdc_dctl_ack_i                           : in     std_logic;
-- Port for MONOSTABLE field: 'Switch to next channel' in reg: 'Channel selection'
    tdc_csel_next_o                          : out    std_logic;
-- Port for BIT field: 'Last channel reached' in reg: 'Channel selection'
    tdc_csel_last_i                          : in     std_logic;
-- Port for BIT field: 'Calibration signal select' in reg: 'Calibration signal selection'
    tdc_cal_o                                : out    std_logic;
-- Port for std_logic_vector field: 'Address' in reg: 'LUT read address'
    tdc_luta_o                               : out    std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Data' in reg: 'LUT read data'
    tdc_lutd_i                               : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Address' in reg: 'Histogram read address'
    tdc_hisa_o                               : out    std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Data' in reg: 'Histogram read data'
    tdc_hisd_i                               : in     std_logic_vector(31 downto 0);
-- Port for MONOSTABLE field: 'Measurement start' in reg: 'Frequency counter control and status'
    tdc_fcc_st_o                             : out    std_logic;
-- Port for BIT field: 'Measurement ready' in reg: 'Frequency counter control and status'
    tdc_fcc_rdy_i                            : in     std_logic;
-- Port for std_logic_vector field: 'Result' in reg: 'Frequency counter current value'
    tdc_fcr_i                                : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Result' in reg: 'Frequency counter stored value'
    tdc_fcsr_i                               : in     std_logic_vector(31 downto 0)
  );
end tdc_wb;

architecture syn of tdc_wb is

signal tdc_cs_rst_dly0                          : std_logic      ;
signal tdc_cs_rst_int                           : std_logic      ;
signal tdc_desh0_int                            : std_logic_vector(31 downto 0);
signal tdc_desl0_int                            : std_logic_vector(31 downto 0);
signal tdc_desh1_int                            : std_logic_vector(31 downto 0);
signal tdc_desl1_int                            : std_logic_vector(31 downto 0);
signal tdc_desh2_int                            : std_logic_vector(31 downto 0);
signal tdc_desl2_int                            : std_logic_vector(31 downto 0);
signal tdc_desh3_int                            : std_logic_vector(31 downto 0);
signal tdc_desl3_int                            : std_logic_vector(31 downto 0);
signal tdc_desh4_int                            : std_logic_vector(31 downto 0);
signal tdc_desl4_int                            : std_logic_vector(31 downto 0);
signal tdc_desh5_int                            : std_logic_vector(31 downto 0);
signal tdc_desl5_int                            : std_logic_vector(31 downto 0);
signal tdc_desh6_int                            : std_logic_vector(31 downto 0);
signal tdc_desl6_int                            : std_logic_vector(31 downto 0);
signal tdc_desh7_int                            : std_logic_vector(31 downto 0);
signal tdc_desl7_int                            : std_logic_vector(31 downto 0);
signal tdc_dctl_req_int                         : std_logic      ;
signal tdc_csel_next_dly0                       : std_logic      ;
signal tdc_csel_next_int                        : std_logic      ;
signal tdc_cal_int                              : std_logic      ;
signal tdc_luta_int                             : std_logic_vector(15 downto 0);
signal tdc_hisa_int                             : std_logic_vector(15 downto 0);
signal tdc_fcc_st_dly0                          : std_logic      ;
signal tdc_fcc_st_int                           : std_logic      ;
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signal eic_idr_int                              : std_logic_vector(9 downto 0);
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signal eic_idr_write_int                        : std_logic      ;
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signal eic_ier_int                              : std_logic_vector(9 downto 0);
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signal eic_ier_write_int                        : std_logic      ;
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signal eic_imr_int                              : std_logic_vector(9 downto 0);
signal eic_isr_clear_int                        : std_logic_vector(9 downto 0);
signal eic_isr_status_int                       : std_logic_vector(9 downto 0);
signal eic_irq_ack_int                          : std_logic_vector(9 downto 0);
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signal eic_isr_write_int                        : std_logic      ;
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signal irq_inputs_vector_int                    : std_logic_vector(9 downto 0);
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signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
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signal rwaddr_reg                               : std_logic_vector(5 downto 0);
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signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal bus_clock_int                            : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_data_i;
  bwsel_reg <= wb_sel_i;
  bus_clock_int <= wb_clk_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      tdc_cs_rst_int <= '0';
      tdc_desh0_int <= "00000000000000000000000000000000";
      tdc_desl0_int <= "00000000000000000000000000000000";
      tdc_desh1_int <= "00000000000000000000000000000000";
      tdc_desl1_int <= "00000000000000000000000000000000";
      tdc_desh2_int <= "00000000000000000000000000000000";
      tdc_desl2_int <= "00000000000000000000000000000000";
      tdc_desh3_int <= "00000000000000000000000000000000";
      tdc_desl3_int <= "00000000000000000000000000000000";
      tdc_desh4_int <= "00000000000000000000000000000000";
      tdc_desl4_int <= "00000000000000000000000000000000";
      tdc_desh5_int <= "00000000000000000000000000000000";
      tdc_desl5_int <= "00000000000000000000000000000000";
      tdc_desh6_int <= "00000000000000000000000000000000";
      tdc_desl6_int <= "00000000000000000000000000000000";
      tdc_desh7_int <= "00000000000000000000000000000000";
      tdc_desl7_int <= "00000000000000000000000000000000";
      tdc_dctl_req_int <= '0';
      tdc_csel_next_int <= '0';
      tdc_cal_int <= '0';
      tdc_luta_int <= "0000000000000000";
      tdc_hisa_int <= "0000000000000000";
      tdc_fcc_st_int <= '0';
      eic_idr_write_int <= '0';
      eic_ier_write_int <= '0';
      eic_isr_write_int <= '0';
    elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          tdc_cs_rst_int <= '0';
          tdc_csel_next_int <= '0';
          tdc_fcc_st_int <= '0';
          eic_idr_write_int <= '0';
          eic_ier_write_int <= '0';
          eic_isr_write_int <= '0';
          ack_in_progress <= '0';
        else
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
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          case rwaddr_reg(5 downto 0) is
          when "000000" => 
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            if (wb_we_i = '1') then
              tdc_cs_rst_int <= wrdata_reg(0);
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              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
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            else
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              rddata_reg(0) <= 'X';
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              rddata_reg(1) <= tdc_cs_rdy_i;
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
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          when "000001" => 
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            if (wb_we_i = '1') then
              tdc_desh0_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desh0_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "000010" => 
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            if (wb_we_i = '1') then
              tdc_desl0_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desl0_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "000011" => 
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            if (wb_we_i = '1') then
              tdc_desh1_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desh1_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "000100" => 
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            if (wb_we_i = '1') then
              tdc_desl1_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desl1_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "000101" => 
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            if (wb_we_i = '1') then
              tdc_desh2_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desh2_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "000110" => 
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            if (wb_we_i = '1') then
              tdc_desl2_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desl2_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "000111" => 
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            if (wb_we_i = '1') then
              tdc_desh3_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desh3_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "001000" => 
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            if (wb_we_i = '1') then
              tdc_desl3_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desl3_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "001001" => 
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            if (wb_we_i = '1') then
              tdc_desh4_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desh4_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "001010" => 
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            if (wb_we_i = '1') then
              tdc_desl4_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desl4_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "001011" => 
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            if (wb_we_i = '1') then
              tdc_desh5_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desh5_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "001100" => 
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            if (wb_we_i = '1') then
              tdc_desl5_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desl5_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "001101" => 
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            if (wb_we_i = '1') then
              tdc_desh6_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desh6_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
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          when "001110" => 
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            if (wb_we_i = '1') then
              tdc_desl6_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desl6_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
420
          when "001111" => 
421 422 423 424 425 426 427
            if (wb_we_i = '1') then
              tdc_desh7_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desh7_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
428
          when "010000" => 
429 430 431 432 433 434 435
            if (wb_we_i = '1') then
              tdc_desl7_int <= wrdata_reg(31 downto 0);
            else
              rddata_reg(31 downto 0) <= tdc_desl7_int;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
436
          when "010001" => 
437 438
            if (wb_we_i = '1') then
            else
439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463
              rddata_reg(7 downto 0) <= tdc_pol_i;
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
464 465 466
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
467
          when "010010" => 
468 469
            if (wb_we_i = '1') then
            else
470
              rddata_reg(31 downto 0) <= tdc_raw0_i;
471 472 473
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
474
          when "010011" => 
475 476
            if (wb_we_i = '1') then
            else
477
              rddata_reg(31 downto 0) <= tdc_mesh0_i;
478 479 480
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
481
          when "010100" => 
482 483
            if (wb_we_i = '1') then
            else
484
              rddata_reg(31 downto 0) <= tdc_mesl0_i;
485 486 487
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
488
          when "010101" => 
489 490
            if (wb_we_i = '1') then
            else
491
              rddata_reg(31 downto 0) <= tdc_raw1_i;
492 493 494
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
495
          when "010110" => 
496 497
            if (wb_we_i = '1') then
            else
498
              rddata_reg(31 downto 0) <= tdc_mesh1_i;
499 500 501
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
502
          when "010111" => 
503 504
            if (wb_we_i = '1') then
            else
505
              rddata_reg(31 downto 0) <= tdc_mesl1_i;
506 507 508
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
509
          when "011000" => 
510 511
            if (wb_we_i = '1') then
            else
512
              rddata_reg(31 downto 0) <= tdc_raw2_i;
513 514 515
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
516
          when "011001" => 
517 518
            if (wb_we_i = '1') then
            else
519
              rddata_reg(31 downto 0) <= tdc_mesh2_i;
520 521 522
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
523
          when "011010" => 
524 525
            if (wb_we_i = '1') then
            else
526
              rddata_reg(31 downto 0) <= tdc_mesl2_i;
527 528 529
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
530
          when "011011" => 
531 532
            if (wb_we_i = '1') then
            else
533
              rddata_reg(31 downto 0) <= tdc_raw3_i;
534 535 536
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
537
          when "011100" => 
538 539
            if (wb_we_i = '1') then
            else
540
              rddata_reg(31 downto 0) <= tdc_mesh3_i;
541 542 543
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
544
          when "011101" => 
545 546
            if (wb_we_i = '1') then
            else
547
              rddata_reg(31 downto 0) <= tdc_mesl3_i;
548 549 550
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
551
          when "011110" => 
552 553
            if (wb_we_i = '1') then
            else
554
              rddata_reg(31 downto 0) <= tdc_raw4_i;
555 556 557
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
558
          when "011111" => 
559 560
            if (wb_we_i = '1') then
            else
561
              rddata_reg(31 downto 0) <= tdc_mesh4_i;
562 563 564
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
565
          when "100000" => 
566 567
            if (wb_we_i = '1') then
            else
568
              rddata_reg(31 downto 0) <= tdc_mesl4_i;
569 570 571
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
572
          when "100001" => 
573 574
            if (wb_we_i = '1') then
            else
575
              rddata_reg(31 downto 0) <= tdc_raw5_i;
576 577 578
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
579
          when "100010" => 
580 581
            if (wb_we_i = '1') then
            else
582
              rddata_reg(31 downto 0) <= tdc_mesh5_i;
583 584 585
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
586
          when "100011" => 
587 588
            if (wb_we_i = '1') then
            else
589
              rddata_reg(31 downto 0) <= tdc_mesl5_i;
590 591 592
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
593
          when "100100" => 
594 595
            if (wb_we_i = '1') then
            else
596
              rddata_reg(31 downto 0) <= tdc_raw6_i;
597 598 599
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
600
          when "100101" => 
601 602
            if (wb_we_i = '1') then
            else
603
              rddata_reg(31 downto 0) <= tdc_mesh6_i;
604 605 606
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
607
          when "100110" => 
608 609
            if (wb_we_i = '1') then
            else
610
              rddata_reg(31 downto 0) <= tdc_mesl6_i;
611 612 613
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
614
          when "100111" => 
615 616
            if (wb_we_i = '1') then
            else
617
              rddata_reg(31 downto 0) <= tdc_raw7_i;
618 619 620
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
621
          when "101000" => 
622 623
            if (wb_we_i = '1') then
            else
624
              rddata_reg(31 downto 0) <= tdc_mesh7_i;
625 626 627
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
628
          when "101001" => 
629 630
            if (wb_we_i = '1') then
            else
631
              rddata_reg(31 downto 0) <= tdc_mesl7_i;
632 633 634
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
635
          when "101010" => 
636
            if (wb_we_i = '1') then
637
              rddata_reg(0) <= 'X';
638
              tdc_dctl_req_int <= wrdata_reg(0);
639
              rddata_reg(1) <= 'X';
640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675
            else
              rddata_reg(0) <= tdc_dctl_req_int;
              rddata_reg(1) <= tdc_dctl_ack_i;
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
676
          when "101011" => 
677 678
            if (wb_we_i = '1') then
              tdc_csel_next_int <= wrdata_reg(0);
679 680
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
681
            else
682
              rddata_reg(0) <= 'X';
683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716
              rddata_reg(1) <= tdc_csel_last_i;
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
717
          when "101100" => 
718
            if (wb_we_i = '1') then
719
              rddata_reg(0) <= 'X';
720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756
              tdc_cal_int <= wrdata_reg(0);
            else
              rddata_reg(0) <= tdc_cal_int;
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
757
          when "101101" => 
758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780
            if (wb_we_i = '1') then
              tdc_luta_int <= wrdata_reg(15 downto 0);
            else
              rddata_reg(15 downto 0) <= tdc_luta_int;
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
781
          when "101110" => 
782 783 784 785 786 787
            if (wb_we_i = '1') then
            else
              rddata_reg(31 downto 0) <= tdc_lutd_i;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
788
          when "101111" => 
789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811
            if (wb_we_i = '1') then
              tdc_hisa_int <= wrdata_reg(15 downto 0);
            else
              rddata_reg(15 downto 0) <= tdc_hisa_int;
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
812
          when "110000" => 
813 814 815 816 817 818
            if (wb_we_i = '1') then
            else
              rddata_reg(31 downto 0) <= tdc_hisd_i;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
819
          when "110001" => 
820 821
            if (wb_we_i = '1') then
              tdc_fcc_st_int <= wrdata_reg(0);
822 823
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
824
            else
825
              rddata_reg(0) <= 'X';
826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859
              rddata_reg(1) <= tdc_fcc_rdy_i;
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
860
          when "110010" => 
861 862 863 864 865 866
            if (wb_we_i = '1') then
            else
              rddata_reg(31 downto 0) <= tdc_fcr_i;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
867
          when "110011" => 
868 869 870 871 872 873
            if (wb_we_i = '1') then
            else
              rddata_reg(31 downto 0) <= tdc_fcsr_i;
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
874
          when "111000" => 
875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912
            if (wb_we_i = '1') then
              eic_idr_write_int <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
913
          when "111001" => 
914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951
            if (wb_we_i = '1') then
              eic_ier_write_int <= '1';
            else
              rddata_reg(0) <= 'X';
              rddata_reg(1) <= 'X';
              rddata_reg(2) <= 'X';
              rddata_reg(3) <= 'X';
              rddata_reg(4) <= 'X';
              rddata_reg(5) <= 'X';
              rddata_reg(6) <= 'X';
              rddata_reg(7) <= 'X';
              rddata_reg(8) <= 'X';
              rddata_reg(9) <= 'X';
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
952
          when "111010" => 
953 954
            if (wb_we_i = '1') then
            else
955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977
              rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0);
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
978 979 980
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
981
          when "111011" => 
982 983 984
            if (wb_we_i = '1') then
              eic_isr_write_int <= '1';
            else
985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007
              rddata_reg(9 downto 0) <= eic_isr_status_int(9 downto 0);
              rddata_reg(10) <= 'X';
              rddata_reg(11) <= 'X';
              rddata_reg(12) <= 'X';
              rddata_reg(13) <= 'X';
              rddata_reg(14) <= 'X';
              rddata_reg(15) <= 'X';
              rddata_reg(16) <= 'X';
              rddata_reg(17) <= 'X';
              rddata_reg(18) <= 'X';
              rddata_reg(19) <= 'X';
              rddata_reg(20) <= 'X';
              rddata_reg(21) <= 'X';
              rddata_reg(22) <= 'X';
              rddata_reg(23) <= 'X';
              rddata_reg(24) <= 'X';
              rddata_reg(25) <= 'X';
              rddata_reg(26) <= 'X';
              rddata_reg(27) <= 'X';
              rddata_reg(28) <= 'X';
              rddata_reg(29) <= 'X';
              rddata_reg(30) <= 'X';
              rddata_reg(31) <= 'X';
1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136
            end if;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_data_o <= rddata_reg;
-- Reset
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      tdc_cs_rst_dly0 <= '0';
      tdc_cs_rst_o <= '0';
    elsif rising_edge(bus_clock_int) then
      tdc_cs_rst_dly0 <= tdc_cs_rst_int;
      tdc_cs_rst_o <= tdc_cs_rst_int and (not tdc_cs_rst_dly0);
    end if;
  end process;
  
  
-- Ready
-- High word value
  tdc_desh0_o <= tdc_desh0_int;
-- Low word value
  tdc_desl0_o <= tdc_desl0_int;
-- High word value
  tdc_desh1_o <= tdc_desh1_int;
-- Low word value
  tdc_desl1_o <= tdc_desl1_int;
-- High word value
  tdc_desh2_o <= tdc_desh2_int;
-- Low word value
  tdc_desl2_o <= tdc_desl2_int;
-- High word value
  tdc_desh3_o <= tdc_desh3_int;
-- Low word value
  tdc_desl3_o <= tdc_desl3_int;
-- High word value
  tdc_desh4_o <= tdc_desh4_int;
-- Low word value
  tdc_desl4_o <= tdc_desl4_int;
-- High word value
  tdc_desh5_o <= tdc_desh5_int;
-- Low word value
  tdc_desl5_o <= tdc_desl5_int;
-- High word value
  tdc_desh6_o <= tdc_desh6_int;
-- Low word value
  tdc_desl6_o <= tdc_desl6_int;
-- High word value
  tdc_desh7_o <= tdc_desh7_int;
-- Low word value
  tdc_desl7_o <= tdc_desl7_int;
-- Value
-- Value
-- High word value
-- Low word value
-- Value
-- High word value
-- Low word value
-- Value
-- High word value
-- Low word value
-- Value
-- High word value
-- Low word value
-- Value
-- High word value
-- Low word value
-- Value
-- High word value
-- Low word value
-- Value
-- High word value
-- Low word value
-- Value
-- High word value
-- Low word value
-- Freeze request
  tdc_dctl_req_o <= tdc_dctl_req_int;
-- Freeze acknowledgement
-- Switch to next channel
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      tdc_csel_next_dly0 <= '0';
      tdc_csel_next_o <= '0';
    elsif rising_edge(bus_clock_int) then
      tdc_csel_next_dly0 <= tdc_csel_next_int;
      tdc_csel_next_o <= tdc_csel_next_int and (not tdc_csel_next_dly0);
    end if;
  end process;
  
  
-- Last channel reached
-- Calibration signal select
  tdc_cal_o <= tdc_cal_int;
-- Address
  tdc_luta_o <= tdc_luta_int;
-- Data
-- Address
  tdc_hisa_o <= tdc_hisa_int;
-- Data
-- Measurement start
  process (bus_clock_int, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      tdc_fcc_st_dly0 <= '0';
      tdc_fcc_st_o <= '0';
    elsif rising_edge(bus_clock_int) then
      tdc_fcc_st_dly0 <= tdc_fcc_st_int;
      tdc_fcc_st_o <= tdc_fcc_st_int and (not tdc_fcc_st_dly0);
    end if;
  end process;
  
  
-- Measurement ready
-- Result
-- Result
-- extra code for reg/fifo/mem: Interrupt disable register
1137
  eic_idr_int(9 downto 0) <= wrdata_reg(9 downto 0);
1138
-- extra code for reg/fifo/mem: Interrupt enable register
1139
  eic_ier_int(9 downto 0) <= wrdata_reg(9 downto 0);
1140
-- extra code for reg/fifo/mem: Interrupt status register
1141
  eic_isr_clear_int(9 downto 0) <= wrdata_reg(9 downto 0);
1142 1143 1144
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
  eic_irq_controller_inst : wbgen2_eic
    generic map (
1145
      g_num_interrupts     => 10,
1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202
      g_irq00_mode         => 0,
      g_irq01_mode         => 0,
      g_irq02_mode         => 0,
      g_irq03_mode         => 0,
      g_irq04_mode         => 0,
      g_irq05_mode         => 0,
      g_irq06_mode         => 0,
      g_irq07_mode         => 0,
      g_irq08_mode         => 0,
      g_irq09_mode         => 0,
      g_irq0a_mode         => 0,
      g_irq0b_mode         => 0,
      g_irq0c_mode         => 0,
      g_irq0d_mode         => 0,
      g_irq0e_mode         => 0,
      g_irq0f_mode         => 0,
      g_irq10_mode         => 0,
      g_irq11_mode         => 0,
      g_irq12_mode         => 0,
      g_irq13_mode         => 0,
      g_irq14_mode         => 0,
      g_irq15_mode         => 0,
      g_irq16_mode         => 0,
      g_irq17_mode         => 0,
      g_irq18_mode         => 0,
      g_irq19_mode         => 0,
      g_irq1a_mode         => 0,
      g_irq1b_mode         => 0,
      g_irq1c_mode         => 0,
      g_irq1d_mode         => 0,
      g_irq1e_mode         => 0,
      g_irq1f_mode         => 0
    )
    port map (
      clk_i                => bus_clock_int,
      rst_n_i              => rst_n_i,
      irq_i                => irq_inputs_vector_int,
      irq_ack_o            => eic_irq_ack_int,
      reg_imr_o            => eic_imr_int,
      reg_ier_i            => eic_ier_int,
      reg_ier_wr_stb_i     => eic_ier_write_int,
      reg_idr_i            => eic_idr_int,
      reg_idr_wr_stb_i     => eic_idr_write_int,
      reg_isr_o            => eic_isr_status_int,
      reg_isr_i            => eic_isr_clear_int,
      reg_isr_wr_stb_i     => eic_isr_write_int,
      wb_irq_o             => wb_irq_o
    );
  
  irq_inputs_vector_int(0) <= irq_ie0_i;
  irq_inputs_vector_int(1) <= irq_ie1_i;
  irq_inputs_vector_int(2) <= irq_ie2_i;
  irq_inputs_vector_int(3) <= irq_ie3_i;
  irq_inputs_vector_int(4) <= irq_ie4_i;
  irq_inputs_vector_int(5) <= irq_ie5_i;
  irq_inputs_vector_int(6) <= irq_ie6_i;
  irq_inputs_vector_int(7) <= irq_ie7_i;
1203 1204
  irq_inputs_vector_int(8) <= irq_isc_i;
  irq_inputs_vector_int(9) <= irq_icc_i;
1205 1206 1207 1208
  rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;