LatticeMico32 Processor

The LatticeMico32 processor is a high-performance 32-bit microprocessor optimized for Lattice Semiconductor field-programmable gate arrays.

*If the processor manual fails to open, see the note at the bottom of this page.

Revision History

Version	Description
3.5	Support added to allow Inline Memories to be generated as non-power-of-two, as long as they are a multiple of 1024 bytes
3.4	Updated to support ispLEVER 7.2 SP1.
3.3	Updated to support ispLEVER 7.2. Added Inline Memory to support on-chip memory connected through a local bus.
3.2	Updated to support ispLEVER 7.1 SP1 Added Memory Type to instruction cache and data cache.
3.1	Updated to support ispLEVER 7.1. Added static predictor to improve the behavior of branches. Added support for optionally mapping the register file to EBRs (on-chip memory). Added support for selecting between distributed RAM and EBRs (pseudo-dual port or true-dual port) for instruction and data caches.
3.0 (7.0 SP2)	Updated to support ispLEVER 7.0 SP2. Fixed incorrect handling of data cache miss in the presence of an instruction cache miss.
1.0	Initial version.

Dialog Box Parameters – General Tab

Parameter	Description
Instance Name	Specifies the name of the LatticeMico32 processor. Alphanumeric values and underscores are supported. The default is LM32.
Settings
Use EBRs for Register File	Uses embedded block RAMS for the register file.
Enable Divide	Enables the divide and modulus instructions (divu, modu).
Enable Sign Extend	Enables the sign-extension instructions (sextb, sexth).
Location of Exception Handlers	Specifies the default value for the vector table. This can be changed by updating the EBA control register or status register. This address must be aligned to a 256-byte boundary, since the hardware ignores the least-significant byte. Unpredictable behavior occurs when the exception base address and the exception vectors are not aligned on a 256-byte boundary.
Multiplier Settings
Enable Multiplier	Enables the multiply instructions (mul, muli).
Enable Pipelined Multiplier (DSP Block if available)	Enables the multiplier using the DSP block, if available.
Enable Multicycle (LUT-based, 32 cycles) Multiplier	Enables the multiplier using LUTs.
Instruction Cache
Instruction Cache Enabled	Determines whether an instruction cache is implemented.
Number of Sets	Specifies the number of sets in the instruction cache. Supported values are 128, 256, 512, 1024.
Set Associativity	Specifies the associativity of the instruction cache. Supported values are 1, 2.
Bytes/Cache Line	Specifies the number of bytes per instruction cache line. Supported values are 4, 8, 16.
Memory Type	Determines the FPGA resource to be used to implement the instruction cache. The decision can be left to the synthesis tool (Auto), or you can select from the following options: Auto – Leaves the implementation of the instruction cache to the synthesis tool. Distributed RAM – Implements the instruction cache as distributed RAM. Dual-Port EBR – Implements the instruction cache as dual-port EBR (two read/write ports). Pseudo Dual-Port EBR – Implements the instruction cache as pseudo-dual-port EBR (one read port and one write port).
Debug Setting
Enable Debug Interface	Includes the debugger stub in the CPU, which is required for debugging.
# of H/W Watchpoint Registers	Specifies the number of hardware watchpoint registers to be used in the debugging process.
Enable Debugging Code in Flash or ROM	Enables you to set hardware breakpoints in read-only memory.
# of H/W Breakpoint Registers	Specifies the number of hardware breakpoint registers to be used in the debugging process.
Enable PC Trace	Enables the Program Counter Trace feature, which enables you to run the program trace during debug to find items in your C or C++ Code during debug, such as breakpoints and exceptions. Refer to Help > Help Contents > C/C++ SPE and Debug > Concepts > Program Counter Trace for more information on Program Counter Trace.
Trace Depth	Enables you to specify the depth of the Program Counter Trace buffer. Refer to Help > Help Contents > C/C++ SPE and Debug > Concepts > Program Counter Trace for more information on Program Counter Trace.
Shifter Settings
Enable Shifter	Enables the multi-bit shift instructions (sr, sri, sru, srui, sl, sli).
Enable Piplined Barrel Shifter	Enables the barrel shifter to be pipelined. The barrel shifter is implemented to perform a shift operation in three cycles.
Enable Multicycle Barrel Shifter (up to 32 cycles)	Enables multi-cycle shift operation for the barrel shifter. The barrel shifter is implemented to shift one bit per cycle and take thirty-two cycles to complete.
Data Cache
Data Cache Enabled	Determines whether a data cache is implemented.
Number of Sets	Specifies the number of sets in the data cache. Supported values are 128, 256, 512, 1024.
Set Associativity	Specifies the associativity of the data cache. Supported values are 1, 2.
Bytes/Cache Line	Specifies the number of bytes per data cache line. Supported values are 4, 8, 16.
Memory Type	Determines the FPGA resource to be used to implement the data cache. The decision can be left to the synthesis tool (Auto), or you can select from the following options: Auto – Leaves the implementation of the data cache to the synthesis tool. Distributed RAM – Implements the data cache as distributed RAM. Dual-Port EBR – Implements the data cache as dual-port EBR (two read/write ports).

Dialog Box Parameters – Inline Memory Tab

Parameter	Description
Instruction Inline Memory
Enable	Enables the instruction inline memory
Instance Name	Specifics the name of the instruction inline memory. Alphanumeric values and underscores are supported. The default is Instruction_IM.
Base Address	Specifies the base address for the instruction inline memory. The default is 0x10000000.
Size of Memory in Bytes	Specifies the size of the instruction inline memory.
Memory File
Initialization File Name	Specifies the name of the memory initialization file for instruction inline memory.
File Format	Specifies the format of the memory initialization file: hex or binary.
Data Inline Memory
Enabled	Enables the data inline memory.
Instance Name	Specifies the name of the data inline memory. Alphanumeric values and underscores are supported. The default is Data_IM.
Base Address	Specifies the base address for the data inline memory. The default is 0x20000000.
Size of Memory in Bytes	Specifies the size of the data inline memory.
Memory File
Initialization File Name	Specifies the name of the memory initialization file for data inline memory.
File Format	Specifies the format of the memory initialization file: hex or binary.

For the revision history of the component RTL files, refer to the header of each component Verilog source file.

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